Need help designing a circuit in Verilog

Define and design a circuit which receives a one-bit wave form and shows on its three one-bit outputs, by one clock cycle long positive impulses, the following events:
-any positive transition of the input signal
-any negative transition of the input signal
-any transition of the input signal

 

[Nikolaos Kavvadias]

Τη Κυριακή, 9 Μαρτίου 2014 8:09:49 μ.μ. UTC+2, ο χρήστης Brian Drummond έγραψε:

On Sun, 09 Mar 2014 03:39:18 -0700, eithriad wrote:



Define and design a circuit which receives a one-bit wave form and shows

on its three one-bit outputs, by one clock cycle long positive impulses,

the following events:

-any positive transition of the input signal -any negative transition of

the input signal -any transition of the input signal



comp.lang.vhdl is probably not the best group for a Verilog question.



- Brian

Indeed, the OP should try comp.lang.vhdl, albeit this homework question looks like a classic one.

 

[Nikolaos Kavvadias]

geez I meant comp.lang.verilog, go figure

 

[Brian Drummond]

On Sun, 09 Mar 2014 03:39:18 -0700, eithriad wrote:

Define and design a circuit which receives a one-bit wave form and shows
on its three one-bit outputs, by one clock cycle long positive impulses,
the following events:
-any positive transition of the input signal -any negative transition of
the input signal -any transition of the input signal

comp.lang.vhdl is probably not the best group for a Verilog question.

- Brian