More Math for the "SETUP"

[Fred Abse]

On Wed, 19 Feb 2014 11:05:48 -0600, amdx wrote:

On 2/19/2014 3:19 AM, Fred Abse wrote:
On Wed, 19 Feb 2014 00:40:33 -0800, Fred Abse wrote:

What you have is the Cgs, and Cgd of the FET, in parallel, making about
1pF

Sorry, that should be 5pF, it's a BF256.

So, I could lower the capacitance at the input with a different fet,

Not by much. FETs come with capacitance included. You might find a better
one, but it'll only be a factor of two, max.

Here comes the Spice:

Version 4
SHEET 1 880 680
WIRE 208 -80 48 -80
WIRE 48 -64 48 -80
WIRE 48 32 48 16
WIRE 208 96 208 -80
WIRE -80 160 -144 160
WIRE 112 160 -16 160
WIRE 160 160 112 160
WIRE 112 208 112 160
WIRE 208 224 208 192
WIRE 336 224 208 224
WIRE -144 240 -144 160
WIRE 208 240 208 224
WIRE 112 336 112 288
WIRE -144 448 -144 320
WIRE 112 448 112 416
WIRE 112 448 -144 448
WIRE 208 448 208 320
WIRE 208 448 112 448
WIRE 112 512 112 448
FLAG 48 32 0
FLAG 112 512 0
FLAG 336 224 out
IOPIN 336 224 Out
FLAG -144 160 in
IOPIN -144 160 In
SYMBOL njf 160 96 R0
SYMATTR InstName J1
SYMATTR Value BF256C
SYMBOL res 192 224 R0
SYMATTR InstName R1
SYMATTR Value 470
SYMBOL res 96 192 R0
SYMATTR InstName R2
SYMATTR Value 10meg
SYMBOL cap -16 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.3p
SYMBOL voltage 48 -80 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 96 320 R0
SYMATTR InstName R3
SYMATTR Value 10meg
SYMBOL voltage -144 224 R0
WINDOW 123 24 106 Left 2
WINDOW 39 24 116 Left 2
SYMATTR Value2 AC 1
SYMATTR SpiceLine Rser=0
SYMATTR InstName V2
SYMATTR Value ""
TEXT -312 232 Left 2 !.ac dec 1000 1k 10meg
TEXT -312 264 Left 2 !.net I(R1) v2
TEXT -424 72 Left 2 !.model BF256C NJF(Beta=1.4m Betatce=-.5 Rd=1 Rs=1 Lambda=4.6m Vto=-3.1\n+ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u\n+ Vk=243.6 Cgd=2.132p M=.3622 Pb=1 Fc=.5 Cgs=2.104p Kf=23.06E-18\n+ Af=1)


And the plot file:

[AC Analysis]
{
Npanes: 2
Active Pane: 1
{
traces: 1 {8388611,0,"Zout(v2)"}
X: ('M',0,1000,0,1e+007)
Y[0]: (' ',0,210,30,540)
Y[1]: (' ',0,-40,20,180)
Log: 1 0 0
GridStyle: 1
PltReal: 1
PltImag: 1
Representation: 2
},
{
traces: 1 {8388610,0,"Zin(v2)"}
X: ('M',0,1000,0,1e+007)
Y[0]: ('M',0,0,2e+006,2.2e+007)
Y[1]: ('M',0,-5.5e+008,5e+007,0)
Log: 1 0 0
GridStyle: 1
PltReal: 1
PltImag: 1
Representation: 2
}
}

--
"Design is the reverse of analysis"
(R.D. Middlebrook)

 

[Fred Abse]

On Wed, 19 Feb 2014 11:00:29 -0600, amdx wrote:

On 2/19/2014 2:40 AM, Fred Abse wrote:
On Tue, 18 Feb 2014 16:51:33 -0600, amdx wrote:

I'm willing to listen, but, I don't see that. The gimmick capacitor,
which is the input capacitor, is a 0.57pf capacitor, will not have 2.9k
of leakage.


First let me see if I understand what you are saying.
For now I'm going to assume the 2.9k -j1.3meg is at 475kHz.

Yes

Are you suggesting, I could take a 0.25pf cap and put it in parallel with
2.9k and this would look like the input to my amp?

No, 2.9k in *series* with 0.25pF

And I could take this same circuit and put it across an inductor on my
Boonton and that would load the same as my amp?

More or less.

It's not leakage, it's the real part of the input impedance, which is
mainly capacitive.

I plead ignorance. If I had just a capacitor wouldn't it be the
capacitance and a very high leakage resistance?

No, no, no. Like capacitor with equivalent series resistance.

Am I mixing up a series and parallel conversion? (2.9k -j1.3meg)

Yes you are. Impedances are series, admittances are parallel.

The magnitude of the input impedance at 1kHz is between 500 and 550
megohms. At 500khZ, it's down to 1.3 megohms. Angle varies from about 87
to 90 degrees, from 1kHz, to 500kHz. Almost wholly capacitive.

What you have is the Cgs, and Cgd of the FET, in parallel, making about
1pF, in parallel with 20 megohms, the whole in series with the
fabricated capacitor.

Also, the proof is in the use, when applied across the inductor the Q
just drops ever so slightly, I don't recall but it was only 1 or 2 Q
points.

Where do you see the low R coming from?

You measured the input impedance as 0.00265 ohms

I got that number by figuring how much R need to be added to reduce Q by
the same amount adding the amp to the Boonton caused.

in series with 2.48pF.

This is how much I needed to increase the cap to bring the Boonton back to
resonance.

Ignoring experimental error, that's where it comes from. The input
impedance is almost wholly capacitive. As a measuring amplifier, it
sucks.

I would think that I want an amplifier input with very low capacitance and
very high Resistance.
So far when I put it across an L on the Boonton, it acts like a
very low capacitance and very high Resistance.

I'll post the curves, if you like.

Is your spice model compatible with LTspice?
I can make a run on that.

Yes, it is.You'll need to bone up on the .net directive, which lets you
plot impedance, admittance, S-paramters, etc.

I'll include a plot file to help.

Curves won't help until I understand the low R and why it doesn't affect
Q on the Boonton.

It does. You said so yourself, 0.00265 ohms, in series with 2.48pF.

That's a giveaway in itself. If you look at the circuit, any capacitance
from the input cannot be greater than the value of the series capacitor
(O.5pf?). I suspect you measured some strays, in addition.

Thanks for playing along with me, Mikek

btw, I did run through the calibration no surprises, except one of the
pots is in a different place, but it did what it should. It now measures
Q just a little lower.

What did you use to measure voltage? A known accurate DVM, I hope.

The internal cap is very tarnished, don't know whether it could be
improve it in any way.

No, leave it alone, tarnished silver conducts almost as well as plain
silver.

Also I noted he says his cap is 0.3pf, I measured a piece of PCB
material with about 0.297 times the area of my gimmick and divided by
0.297 to get the 0.56pf. I thought I had made my cap smaller than his,
apparently not.

You're into the realm where strays dominate. You need thick straps to
connect, and keep the DUT away from sources of stray capacitance. Good
practice dictates that you make a test fixture, and measure that without a
specimen, first, then with the specimen, and subtract. Similar to weighing
a container empty, then full.

--
"Design is the reverse of analysis"
(R.D. Middlebrook)