R
rickman
Guest
On 7/26/2016 8:11 PM, Kevin Neilson wrote:
> I think Celoxica is defunct.
So there it is!
--
Rick C
> I think Celoxica is defunct.
So there it is!
--
Rick C
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K
Kevin Neilson
Guest
Even with your example of a matrix multiplication, there is still a lot to figure out. For one thing, you usually have to fold the multiplication because you don't have the resources to do the whole thing in parallel. The Matlab->gates tool that I used once is long gone.
I just spent several days implementing a design that I modeled in two lines of Matlab code. For a tool to have converted those two lines into a good hardware implementation would've been difficult.
I just spent several days implementing a design that I modeled in two lines of Matlab code. For a tool to have converted those two lines into a good hardware implementation would've been difficult.
K
Kevin Neilson
Guest
The high-level design tools I've used weren't very abstracted. To make something work well, I had to keep moving to lower levels of abstraction. In tool that was supposed to be high-level I found myself instantiating DSP48s. Not very abstract.
R
rickman
Guest
On 7/27/2016 1:33 PM, Jecel wrote:
At least with open source tools you can't be disappointed by a total
lack of support. My installation of Lattice Diamond errors out when I
perform synthesis and I can't get any help from the vendor support... at
all!
--
Rick C
On Wednesday, July 27, 2016 at 11:41:11 AM UTC-3, rickman wrote:
On 7/26/2016 8:11 PM, Kevin Neilson wrote:
I think Celoxica is defunct.
So there it is!
Celoxica was a very successful company that was bought out by
a much larger competitor and immediately shut down. This left
many customers who loved the product without any good options.
And this is why I refuse to use non open source tools no matter
what advantages they claim to have. You can't know if they will
still be available tomorrow. The exception (for now) is the
vendor tools for generating the FPGA bitfiles.
At least with open source tools you can't be disappointed by a total
lack of support. My installation of Lattice Diamond errors out when I
perform synthesis and I can't get any help from the vendor support... at
all!
--
Rick C
T
Theo Markettos
Guest
Kevin Neilson <kevin.neilson@xilinx.com> wrote:
I agree, you can't expect the tool to just do it - there are many things
that need to be tweaked. But those are architectural design choices, which
are different from writing Verilog or VHDL. By all means expose the
tradeoffs to the designer in a way they understand, just don't make them
write HDL. Software folks are familiar with the idea of different data
structures having difference performance qualities. But by and large a
serial 'program' isn't a helpful way to expose tradeoffs to either the
software or hardware engineer.
As I said, this ignores the elephant in the room that is communication.
Your C code has this illusion that it lives in a flat uniform memory space
because it's behind a cache, an MMU, a prefetcher and a standard library,
that do a lot of work (in terms of time, area and power) to make it look
that way. To get good performance, you need both a way to write the compute
and a way to move the data around to the right place at the right time.
'HLS' tools are usually poor at handling that: I don't know a HLS 'C to
gates' tool that it would make sense to write a cache in, for example.
Theo
Even with your example of a matrix multiplication, there is still a lot to
figure out. For one thing, you usually have to fold the multiplication
because you don't have the resources to do the whole thing in parallel.
The Matlab->gates tool that I used once is long gone.
I just spent several days implementing a design that I modeled in two
lines of Matlab code. For a tool to have converted those two lines into a
good hardware implementation would've been difficult.
I agree, you can't expect the tool to just do it - there are many things
that need to be tweaked. But those are architectural design choices, which
are different from writing Verilog or VHDL. By all means expose the
tradeoffs to the designer in a way they understand, just don't make them
write HDL. Software folks are familiar with the idea of different data
structures having difference performance qualities. But by and large a
serial 'program' isn't a helpful way to expose tradeoffs to either the
software or hardware engineer.
As I said, this ignores the elephant in the room that is communication.
Your C code has this illusion that it lives in a flat uniform memory space
because it's behind a cache, an MMU, a prefetcher and a standard library,
that do a lot of work (in terms of time, area and power) to make it look
that way. To get good performance, you need both a way to write the compute
and a way to move the data around to the right place at the right time.
'HLS' tools are usually poor at handling that: I don't know a HLS 'C to
gates' tool that it would make sense to write a cache in, for example.
Theo