matrix generation

D

Damian Drewulski

Guest
Hi there,
i have some problem. I need to get sorting net. 40 comparators in 81
line.

First i declared matrix:

type wire is array (0 to 81) of std_logic_vector (7 downto 0);
type connections is array (0 to 81) of wire;

Then i'm trying to generate a net of comparators.

component comparator
port(
clk : in std_logic;
rst : in std_logic;

A_in : in std_logic_vector (7 downto 0);
B_in : in std_logic_vector (7 downto 0);

A_out : out std_logic_vector (7 downto 0);
B_out : out std_logic_vector (7 downto 0)
);
end component;

sorting_net : for i in 0 to 40 generate
ins: for j in (0 to 81) generate
comparatorx : comparator port map(clk, rst, connections(i*2) of
wire(j), connections(i*2 + 1) of wire (j), connections(i*2) of wire (j
+1), connections(i*2 + 1) of wire (j+1));
end generate;
end generate;

And after that i get few errors. I use quartus.
Anyone could help me?

best wishes,
Damian
 
On Nov 10, 2:57 pm, Damian Drewulski <damianne...@gmail.com> wrote:
Hi there,
i have some problem. I need to get sorting net. 40 comparators in 81
line.

First i declared matrix:

        type wire is array (0 to 81) of std_logic_vector (7 downto 0);
        type connections is array (0 to 81) of wire;

Then i'm trying to generate a net of comparators.

component comparator
        port(
        clk : in std_logic;
        rst : in std_logic;

   A_in : in std_logic_vector (7 downto 0);
        B_in : in std_logic_vector (7 downto 0);

        A_out : out std_logic_vector (7 downto 0);
        B_out : out std_logic_vector (7 downto 0)
);
end component;

sorting_net : for i in 0 to 40 generate
        ins: for j in (0 to 81) generate
                comparatorx : comparator port map(clk, rst, connections(i*2) of
wire(j), connections(i*2 + 1) of wire (j), connections(i*2) of wire (j
+1), connections(i*2 + 1) of wire (j+1));
        end generate;
end generate;

And after that i get few errors. I use quartus.
Anyone could help me?

best wishes,
Damian
You have to connect the IO of the instantiation to signals or IO, you
cannot connect them to types.

You need to declare a signal of type "connections" and connect
everything to that.
 

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