magnetic field

[Chuck Harris]

Watson A.Name - "Watt Sun, the Dark Remover" wrote:

You have to give the poor little MPF102 a break, and bias it properly.
It needs about -5V Vgs to operate, so you need to up your source

resistor

to be equal to your drain resistor, if you want it to run at 9V.


Well, that was what I mentioned in another followup. According to the
specs, the MPF102 can have a Vgs of anywhere from .5V to 7.5V; that's a
ratio of fifteen to one. In the case of the FET I chose, it seems to be
working pretty good at about 1.5 V. But I'll vary it to see what effect
it has.

The problem is the actual gain of the stage is: Av = -RL/gm, where
RL is the total load, and as such is the parallel combination of the drain
resistor, and the resistance of the FET, rs. In the linear region, rs
changes depending on where you bias the FET. rs is low when Vgs is near
zero, and high when Vgs is very negative. To get maximal gain, you
want rs to be high. Like all things, you have to reach a compromise.

The 330k and 1uF sections of my schem, and the 1M and .33uF sections of
your schem have the same net effect because they are both loaded by the
gate, which is nearly infinite impedance, so the gate is negligible.
And since in both cases the impedance of the RC net is more than ten
times the drain load resistor, the RC net has negligible loading effect
in the drain resistor. Do you agree with this? If so, then it seems
that there should be no need to change from 330k and 1 uF to 1M and .33
uF RC sections.

I arranged the phase circuit the way I did to eliminate the need for the
extra isolation capacitor, and gate resistor. The values you used are
fine. I prefer high impedance because it makes for a smaller network.

So after all this, it comes down to the number of sections, mine with
four, and yours with three. I tried the three sections, and I could
barely tell that there was some overshoot on the output waveform, it was
_very_ damped. So there was a serious need for more gain or less
attenuation. So I went with four sections to get less attenuation.

Well, if you are really concerned about attenuation, you can use the
classic technique of making each section of the network 10x the impedance
of the last. eg:

-----0.0033---o---0.033---o---0.33---o---gate
| | |
10K 100K 1M
| | |
G G G

Then you will only need a gain of 9 or 10 to overcome the loss of the
phase shift network. (This technique works because it reduces
the loading on the previous stage, and gets you closer to the theoretical
stage where there is no loading on the output of any stage.)

And I tried the 22k drain load resistor, but it was still too low.
Finally when I got up into the high 20s I started to see some life in
the damped oscillation. At 33k it finally was able to sustain
oscillations. What I need to do now is fiddle with the source bias
resistor to get the waveform to clip symmetrically. So your suggestion
of changing the Vgs looks like it'll be one key to get the waveform
looking reasonable.

Getting the gate biased into the correct region that gives a high
value of rs is everything! If I wanted to operate with a higher
voltage supply, I would then reduce Rs from 22K to 12K. That would give
me clean operation at 15V, but sacrifice operation at 9V.

-Chuck Harris

 

[Dimitrios Tzortzakakis]

Yoroshiku onegai shimasu!Watashi wa koko ni imasu yo!Mizu tsumetai
desho?Iie, sonnani tsumetaku arimasen yo.
(Mean:I need you to be in favour with me,Here am I,is the water cold?It's
not that cold.)

--
Tzortzakakis Dimitriďs
major in electrical engineering, freelance electrician
FH von Iraklion-Kreta, freiberuflicher Elektriker
dimtzort AT otenet DOT gr
Ď "John Woodgate" <jmw@jmwa.demon.contraspam.yuk> Ýăńářĺ óôď ěŢíőěá
news:GpVEsaDa2b2BFw8v@jmwa.demon.co.uk...

I read in sci.electronics.design that nooneinparticular314159@yahoo.com
wrote (in <1104787856.310883.276250@z14g2000cwz.googlegroups.com&gt about
'Solution to television reception problem', on Mon, 3 Jan 2005:

In other words, anything I do needs to be inside my own apt, and should
not be very expensive.

Given that constraint, there is no solution.

But do other people in the building have the same problem? If so, a
joint approach to the landlord might get you an antenna on the roof, and
a distribution system to each apartment. You may have to contribute some
$$, but shared out, the cost should not be unsupportable.

In Japan, it used to be a legal requirement that if a new building
created a TV shadow, its owners had to provide a remedy free of charge,
but I don't think it applies in any other country, and maybe not even in
Japan now.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

 

[Mark]

Put a dimmer control on the bulbs.

That way you can turn them down or up as the mood strike you.

Even though a dimmer works as a phase controller , it WILL solve your
problem. When you dim the bulbs down they will last longer because the
RMS voltage is decreased.


Mark

 

[Pinkerbot]

Thanks! This seems to be just what we were looking for.

 

Actually, there is a really easy way of controlling relays using
parallel port over ethernet, using a print server. You just have to
hotwire a couple of pins, and send the commands down the LPR port.
Hardware cost is about Ł27 ($45).

See
http://www.tekkies.co.uk/index.php?option=content&task=view&id=17&Itemid=28
Shandy

 

[Chuck Harris]

Watson A.Name - "Watt Sun, the Dark Remover" wrote:

No. There is _no_ voltage drop across the gate resistor because the
gate is essentially an open, the leakage current is literally picoamps.
The cap will not help and is not needed.

Come on Watson, there has to be a signal on the gate. A PSO is an
inverting amplifier with a 180 degree lead/lag network feeding back
output signal to the input.

If you truly have no signal, you have no oscillation.

So if
you put a 1 uF capacitor in series with the 10 megs and the

combination in series with the

probe tip, you will not be upsetting the bias, since there won't be a

DC path through the



Again, the capacitor is of no help. The problem is that the impedance
at the gate is 4.3M, which is so high that if you put a 11M probe on it,
the added attenuation will cause the FET to stop oscillating.

There are two modes of operation going on in this oscillator: The DC biasing
with its feedback stabilization, and the AC signal, with its feedback network.

The DC biasing is caused by the voltage drop in the source resistor.
As the FET tries to draw too much iGD, the voltage drop on Rs increases,
putting the gate more into the cutoff, or OFF, region, which reduces the voltage
drop on Rs, which puts the gate less into the cutoff region, ... Because your
source capacitor is huge, this will be a measurable effect all by itself,
albeit a very damped one, as the bias circuit is a source follower and has a DC
gain that is *always* less than one (so it is always stable).

The AC signal path is the one that has fairly high gain. It must have a gain
of at least 29x for my circuit to work. This is easily measurable, remove your
phase shift network, and stick a capacitor coupled, 100 millivolt signal (any
audio frequency will do) into the gate, and measure the signal on the drain.

For your circuit to operate, you had better see a couple of volts on your drain!

(Conversely, if your oscillator is working, it must have about 100 mv on your
gate.)

Your gain is: Av = -Vo/Vi, we are only interested in AC voltages!


-Chuck Harris

 

[John Woodgate]

I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt
Sun, the Dark Remover" <NOSPAM@dslextreme.com> wrote (in <10ttkm9cs4cjm1
5@corp.supernews.com&gt about 'Why Can't I get This FET To Oscillate', on
Fri, 7 Jan 2005:

If I go to a 1 uF the reactance
will be 240k, which is more than 5 percent of the 4.3M gate resistor,
and adds appreciably to the attenuation. In this circuit, with its
damped osc problem, that can make the difference between sustained
oscillation and damped.

I don't think so. 240 kohms in quadrature with 4.3 Mohm is 4.3066..
Mohms. The attenuation is quite negligible.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

 

[John Popelish]

Jim Thompson wrote:

On Sun, 02 Jan 2005 16:50:39 -0500, John Popelish <jpopelish@rica.net
wrote:

John Larkin wrote:

On Sun, 02 Jan 2005 15:39:48 -0500, John Popelish <jpopelish@rica.net
wrote:

You can get a bit less loss out of the phase shift network if you
stage the impedances. Say, 2.2 uf and 150k for the left one, 1uf and
300k for the second one and .47 uf 680k for the right one.

Cool. In the limiting case where each RC doesn't load the one before,
three RCs give 180 degrees shift with a gain of 0.125.

If you did 4 RCs like this, 45 degrees each, gain is 0.25!

Etcetera, I think.

John

Of course, the ultimate is to put a follower between each stage.

Or use a proper oscillator ;-)

Just trying to make the problem stand out in sharper relief.

I like the version that puts 3 lossy integrators (resistor across the
cap) in a ring with an AGC to control amplitude. Spreads the
tolerance problems around, too.

--
John Popelish

 

[Jim Thompson]

On Tue, 4 Jan 2005 05:56:29 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\"" <NOSPAM@dslextreme.com> wrote:

[snip]

Mine is blinking away merrily. I put an EF on it and a blue LED, so I
can watch it doing its thing. On another BJT one I made, I put an amp
on one of the other phases, so I get this 'one-two..' flip-flop type of
flashing from the LEDs.

Sheeeesh! Was all this posting about phase-shift oscillators just to
accomplish a blinking LED?

A phase-shift oscillator is normally built to create SINE waves...
certainly NOT the most efficient way to blink LEDs at a slow rate.

Sheeeesh!

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Watson A.Name - \"Watt Su]

"Chuck Harris" <cf-NO-SPAM-harris@erols.com> wrote in message
news:2aWdnVJT_9uqAEfcRVn-1w@rcn.net...

Watson A.Name - "Watt Sun, the Dark Remover" wrote:

You have to give the poor little MPF102 a break, and bias it
properly.
It needs about -5V Vgs to operate, so you need to up your source

resistor

to be equal to your drain resistor, if you want it to run at 9V.


Well, that was what I mentioned in another followup. According to
the
specs, the MPF102 can have a Vgs of anywhere from .5V to 7.5V;
that's a
ratio of fifteen to one. In the case of the FET I chose, it seems
to be
working pretty good at about 1.5 V. But I'll vary it to see what
effect
it has.

The problem is the actual gain of the stage is: Av = -RL/gm, where
RL is the total load, and as such is the parallel combination of the
drain
resistor, and the resistance of the FET, rs. In the linear region, rs
changes depending on where you bias the FET. rs is low when Vgs is
near
zero, and high when Vgs is very negative. To get maximal gain, you
want rs to be high. Like all things, you have to reach a compromise.

The 330k and 1uF sections of my schem, and the 1M and .33uF sections
of
your schem have the same net effect because they are both loaded by
the
gate, which is nearly infinite impedance, so the gate is negligible.
And since in both cases the impedance of the RC net is more than ten
times the drain load resistor, the RC net has negligible loading
effect
in the drain resistor. Do you agree with this? If so, then it
seems
that there should be no need to change from 330k and 1 uF to 1M and
..33
uF RC sections.

I arranged the phase circuit the way I did to eliminate the need for
the
extra isolation capacitor, and gate resistor. The values you used are
fine. I prefer high impedance because it makes for a smaller network.


So after all this, it comes down to the number of sections, mine
with
four, and yours with three. I tried the three sections, and I could
barely tell that there was some overshoot on the output waveform, it
was
_very_ damped. So there was a serious need for more gain or less
attenuation. So I went with four sections to get less attenuation.

Well, if you are really concerned about attenuation, you can use the
classic technique of making each section of the network 10x the
impedance
of the last. eg:

-----0.0033---o---0.033---o---0.33---o---gate
| | |
10K 100K 1M
| | |
G G G

Umm, don't you mean:


-----33u---o---3.3u----o---0.33u---o---gate
| | |
10K 100K 1M
| | |
G G G

In which case it looks like the network will be a substantial load on
the drain. So it would then be necessary to put an emitter follower on
the drain just to drive the network. Maybe it would be better to change
it to: (Or even higher)

----3.3u---o---.33u----o---.033u---o---gate
| | |
100K 1M 10M
| | |
G G G

Seems that the nice thing about using a four section network is that
each section does 45 degrees. That would make the reactance equal to
the resistance. And this simplifies things a bit.

But others seem to favor the lag network over the lead network. For
BJTs I've found that the lead network seems to have less waveform
distortion than the lag.

Then you will only need a gain of 9 or 10 to overcome the loss of the
phase shift network. (This technique works because it reduces
the loading on the previous stage, and gets you closer to the
theoretical
stage where there is no loading on the output of any stage.)


And I tried the 22k drain load resistor, but it was still too low.
Finally when I got up into the high 20s I started to see some life
in
the damped oscillation. At 33k it finally was able to sustain
oscillations. What I need to do now is fiddle with the source bias
resistor to get the waveform to clip symmetrically. So your
suggestion
of changing the Vgs looks like it'll be one key to get the waveform
looking reasonable.

Getting the gate biased into the correct region that gives a high
value of rs is everything! If I wanted to operate with a higher
voltage supply, I would then reduce Rs from 22K to 12K. That would
give
me clean operation at 15V, but sacrifice operation at 9V.

-Chuck Harris

 

[Watson A.Name - \"Watt Su]

"Jim Thompson" <thegreatone@example.com> wrote in message
news:2mslt05vl3k0vo71q63tio8k9ov7ogkd29@4ax.com...

On Tue, 4 Jan 2005 05:56:29 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\"" <NOSPAM@dslextreme.com> wrote:

[snip]

Mine is blinking away merrily. I put an EF on it and a blue LED, so
I
can watch it doing its thing. On another BJT one I made, I put an
amp
on one of the other phases, so I get this 'one-two..' flip-flop type
of
flashing from the LEDs.



Sheeeesh! Was all this posting about phase-shift oscillators just to
accomplish a blinking LED?

A phase-shift oscillator is normally built to create SINE waves...
certainly NOT the most efficient way to blink LEDs at a slow rate.

Sheeeesh!

Why don't you just mind your own OT political discussion business.

If you don't behave, we'll send more rainstorms over you. Heh.

...Jim Thompson
--

 

[Watson A.Name - \"Watt Su]

"The Phantom" <phantom@aol.com> wrote in message
news:0islt0p0s2h0cs5h6aq12chl25bqah0isi@4ax.com...

On Tue, 4 Jan 2005 05:56:29 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:



I don't think a ratio of ten is realistic, and 100 is out of the
quwstion. The ratio of two or three seems to be what others have
suggested and more realistic.

Confirming what John Popelish says, my calculations indicate a
required amplifier gain
of -16 for the 1:2:4 impedance taper, and a required gain of -12.8519
for the 1:3:9 taper.

For the 4 section version with a 1:2:4:8 taper, the required gain
is -8.6178 and for
the version with a 1:3:9:27 taper, the required gain is -6.659.

According to http://home.earthlink.net/~doncox/wec/Oscillators.html the
gain needed for four equal sections is 16. But that includes stage
loading. Something said there about it would be 4 if loading is
neglected.

Last night, I put an additonal diode (3 total) in series with the drain
resistor, which I reduced to 1.5k. This gives a drop of 1.77V. As
power is applied and the capacitors charge up, which takes several
minutes, it starts oscillating. But the caps continue to charge, and
after several more minutes, the oscillations damp out. The drain
voltage rises to over 7V, too high. I think I've gone past the optimum
point, I'll have to pot a pot in there and adjust to see where it'll
keep oscillating.

So far, this is what I've got.


+9V
|
.-.
| |
33k| |
'-'
|
.----------------------------------------------o----o Vout
| |
| o-------o |
.-. | | |
| | | 4.3M .-. |
| | 330k === | | +------o V out
'-' GND | | |
| '-' |
| +|| | |-
o---/\/\---o---/\/\--o--/\/\----o---||--o--->| JFET MPF102
| | | | || |-
| 330k | 330k | 330k | 10u |
| | | | o----.
| | | | | |
| | | | .-. |
--- 1.0u --- 1.0u --- 1.0u --- 1.0u | | | +
--- --- --- --- 1.5k | | --- 2 caps
| | | | See '-' --- 3200uF
| | | | note | | total
=== === === === below === ===
GND GND GND GNF GND GND

Note: 3 BAV21 diodes are in series with the 1.5k to give another 1.6V
drop, to
put more negative bias on the gate. Total drop across all is about
1.77V.

As of late Sun nite, with the above values, I got it to oscillate.
Finally.

But as of Tuesday Eve, Dec 4, 05, the caps keep charging up, and the
oscs die out.
I think I've gone past the optimum bias point.

The one I'm using, with four equal sections seems to be about the
only
'non-classic' version that has been in literature. I can't remember
ever seeing a 'non-classic' version of a PSO that used unequal
sections.
Not to say that it can't be done, tho. But I'd prefer to experiment
with something on which an analysis has been done.

Mine is blinking away merrily. I put an EF on it and a blue LED, so
I
can watch it doing its thing. On another BJT one I made, I put an
amp
on one of the other phases, so I get this 'one-two..' flip-flop type
of
flashing from the LEDs.

 

[Chuck Harris]

Watson A.Name - "Watt Sun, the Dark Remover" wrote:

"Chuck Harris" <cf-NO-SPAM-harris@erols.com> wrote in message

of the last. eg:

-----0.0033---o---0.033---o---0.33---o---gate
| | |
10K 100K 1M
| | |
G G G


Umm, don't you mean:


-----33u---o---3.3u----o---0.33u---o---gate
| | |
10K 100K 1M
| | |
G G G

Yes, that's what I meant. Sorry for the lisdexya.

The MPF102 is really too wimpy for this circuit, an MPF112/HEP801
with the appropriate bias changes would work MUCH better

In which case it looks like the network will be a substantial load on
the drain. So it would then be necessary to put an emitter follower on
the drain just to drive the network. Maybe it would be better to change
it to: (Or even higher)

----3.3u---o---.33u----o---.033u---o---gate
| | |
100K 1M 10M
| | |
G G G

That would work fine.... no emitter follower necessary.

Seems that the nice thing about using a four section network is that
each section does 45 degrees. That would make the reactance equal to
the resistance. And this simplifies things a bit.

But others seem to favor the lag network over the lead network. For
BJTs I've found that the lead network seems to have less waveform
distortion than the lag.

If you can see *any* distortion using an oscilloscope, your oscillator
is not running as a phase-shift oscillator. The one I breadboarded gives
a perfect looking sinewave. I would bet that if I hooked it up to my
distortion analyzer it would be well under 1%

See John Jardine's note about my original circuit. When I breadboarded
it with the 100uf source cap, and the 22K drain it was oscillating in
a wierd way. Changing the drain resistor to 47K, and upping the cap
stopped that and it started to behave as a real phase-shift oscillator
should... Clean and high amplitude. It also runs from 7v to 15v with
no problems.

-Chuck

 

[Watson A.Name - \"Watt Su]

"The Phantom" <phantom@aol.com> wrote in message
news:0uvmt0t2t403h2l2k3u7pmu9f9jejm6h60@4ax.com...

On Wed, 5 Jan 2005 01:00:46 -0000, "john jardine"
john@jjdesigns.fsnet.co.uk> wrote:

Looking up the MPF102 specs, I see a minimum Gm of 2000 umhos with
Vgs of zero and
about 10 umhos output conductance. With a 22k drain resistor and no
source resistance,
this would give a gain of .002/(1/22000+1/100000) = 36. This would be
with a drain
current equal to Idss, but with 22k in the drain we need a drain
current of less than 1mA.
Otherwise we would have to put an active current source in the drain
to get such a high
incremental resistance without reducing Vds to nearly zero. The spec
sheet curves
indicate that for a drain current of .2mA, the Gm is about 1000 umhos,
so we would have a
gain of only 18. At any rate, the source resistor bypassing would
have to be a lot better
than 100 uF provides to get the amplifier phase shift to be
negligible. My MicroCap
simulation verifies your result, but I think a typical MPF102 should
be able to provide
enough gain even with a properly bypassed source resistor to oscillate
with a 4 section
tapered phase shift network.

Well, I've simulared your simulation with the Real Thing, which has four
sections. It does oscillate. Maybe my mistake is to use such a large
(3200uF) source bypass cap. I've got a 33k drain resistor, with less
than 6.6V (which is 200 uA) across it.

I think that the series combination of the 33k drain resistor, the four
220k resistors, and the 4.3M gate resistor, and the 10 uF cap, takes
several minutes to charge the cap. One time constant is about 56.5
seconds, or over 1 minute. This and the source byp cap are causing the
osc's to damp out after several minutes. I'm going to have to reduce
them and see if it helps.

 

[The Phantom]

On Thu, 6 Jan 2005 01:48:37 -0800, "Watson A.Name - \"Watt Sun, the Dark Remover\""
<NOSPAM@dslextreme.com> wrote:

"The Phantom" <phantom@aol.com> wrote in message
news:citpt0pefseqd290tcgheag2v1ir44b1r4@4ax.com...
On Wed, 5 Jan 2005 23:39:15 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:


"The Phantom" <phantom@aol.com> wrote in message
news:qp2nt0551477oaivfo6574oshvoc4iac2g@4ax.com...
On Tue, 4 Jan 2005 21:36:26 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\""
NOSPAM@dslextreme.com> wrote:

G

Umm, don't you mean:


-----33u---o---3.3u----o---0.33u---o---gate
| | |
10K 100K 1M
| | |
G G G

In which case it looks like the network will be a substantial load
on
the drain. So it would then be necessary to put an emitter
follower
on
the drain just to drive the network. Maybe it would be better to
change
it to: (Or even higher)

----3.3u---o---.33u----o---.033u---o---gate
| | |
100K 1M 10M
| | |
G G G

Seems that the nice thing about using a four section network is
that
each section does 45 degrees. That would make the reactance equal
to
the resistance. And this simplifies things a bit.

But others seem to favor the lag network over the lead network.

One disadvantage of the lead network is that the transmission
through the network is not
rolled off at high frequencies, increasing the possibility of
parasitic VHF oscillations.

Would you measure the gain from the gate to drain while it's
oscillating so we can see
what kind of performance might be possible with this particular
FET?
Be sure to use a
high impedance probe on the gate.

I have only a 1M 10x probe for my 'scope.

Since you are getting oscillations at such a low frequency, you can
just put a 10 meg
resistor in series with the probe tip and measure the ac voltage at
gate and drain and
take the ratio. The probe need not be compensated for this
measurement.

I still have a couple problems. I've been watching (Well TV too) this
thing, and after 40 minutes it's damped out again. I changed the bias
resistor, and it takes maybe ten minutes to ramp up, then it osillates
for another 10 or 20 min, then it takes another ten mins to die out. So
even if I take a measurement, it isn't stable enough to be certain the
reading is right. I'm still working on getting the bias right.

But if I put a 10M res in series with the probe, I still have a problem.
The gate resistor is 4.3M, so I've effectively got a parallel
combination that's about 3.1M and as it's barely oscillating w/o the
probe, I would guess it won't osc at all with it. Not to mention it's
still loading down the gate.

Put a *non-electrolytic* capacitor of a few tenths of a microfarad in series with the
10 Meg resistor as well, and then the DC bias won't be upset. And you could use *several*
10 Meg resistors. As long as your scope has enough gain so you can get a useable
indication you should be able to make the measurement.

I'm thinking it might be better to put a .8M in series with the gate res
to make a 10:1 divider and take the measurement across that res.

For
BJTs I've found that the lead network seems to have less waveform
distortion than the lag.

 

[The Phantom]

On Thu, 6 Jan 2005 05:56:53 -0800, "Watson A.Name - \"Watt Sun, the Dark Remover\""
<NOSPAM@dslextreme.com> wrote:

Would you measure the gain from the gate to drain while it's
oscillating so we can see
what kind of performance might be possible with this particular
FET?
Be sure to use a
high impedance probe on the gate.

I have only a 1M 10x probe for my 'scope.

Since you are getting oscillations at such a low frequency, you
can
just put a 10 meg
resistor in series with the probe tip and measure the ac voltage at
gate and drain and
take the ratio. The probe need not be compensated for this
measurement.

I still have a couple problems. I've been watching (Well TV too)
this
thing, and after 40 minutes it's damped out again. I changed the
bias
resistor, and it takes maybe ten minutes to ramp up, then it
osillates
for another 10 or 20 min, then it takes another ten mins to die out.
So
even if I take a measurement, it isn't stable enough to be certain
the
reading is right. I'm still working on getting the bias right.

But if I put a 10M res in series with the probe, I still have a
problem.
The gate resistor is 4.3M, so I've effectively got a parallel
combination that's about 3.1M and as it's barely oscillating w/o the
probe, I would guess it won't osc at all with it. Not to mention
it's
still loading down the gate.

Put a *non-electrolytic* capacitor of a few tenths of a microfarad
in series with the
10 Meg resistor as well, and then the DC bias won't be upset. And you
could use *several*
10 Meg resistors. As long as your scope has enough gain so you can
get a useable
indication you should be able to make the measurement.

I don't think you understand what's happening. The JFET's gate has zero
volts bias across the gate resistor, because it's, well, a FET, not a
BJT. And at the freq we're dealing with here, the few tenths of a uF
will be essentially an open.

What I'm suggesting is a way to measure the gain of your FET when the circuit is
oscillating. The probe with a 10 meg resistor in series with the probe tip would give
about 11 megs DC resistance which would upset your bias when connected to the gate. So if
you put a 1 uF capacitor in series with the 10 megs and the combination in series with the
probe tip, you will not be upsetting the bias, since there won't be a DC path through the
combination (neglecting the leakage of the cap, which if it is a film cap, will be very
low). I believe your frequency of oscillation is *about* 1 Hz. The impedance of a 1 uF
capacitor at 1 Hz is 159K ohms which is negligible compared to the 10 meg resistor, so you
should be able to get a usable signal to the scope. The change in calibration factor of
the scope won't matter, since you will measure the amplitude of the approximately 1 Hz
sine wave at the gate and at the drain with the same probe plus 10 meg (or more) and 1 uF
in series with the probe tip. Just take the ratio of the amplitude at the drain to that
at the gate and that's your amplifier gain under actual operating conditions.

I'm thinking it might be better to put a .8M in series with the gate
res
to make a 10:1 divider and take the measurement across that res.

For
BJTs I've found that the lead network seems to have less
waveform
distortion than the lag.

 

[John Woodgate]

I read in alt.binaries.schematics.electronic that Watson A.Name - "Watt
Sun, the Dark Remover" <NOSPAM@dslextreme.com> wrote (in <10tum2m2i0367d
f@corp.supernews.com&gt about 'Why Can't I get This FET To Oscillate', on
Fri, 7 Jan 2005:

Not only is there some attenuation, there is also the phase shift.

3.2 degrees.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

 

[The Phantom]

On Sat, 8 Jan 2005 09:45:14 -0800, "Watson A.Name - \"Watt Sun, the Dark Remover\""
<NOSPAM@dslextreme.com> wrote:

I made up a jig with a socket for the FETs. I used two 9V batts, one
for the drain supply and the other for the neg bias on the gate. Below
are the values I got for the Vgs(off). The data sheet uses 15V on the
drain, but I used only 9VDC, so it isn't exactly the same, but close.
It was really difficult to get the 100k neg V adjust pot to stay put at
2 nA (which was 2 mV across a 1M rsistor). I measured a total of 26
MPF102s, some Moto's, some Signetics, some not marked with a logo.

MPF102 (26 total measured) Jan 7, 2005
Vgs(off) @ Vds=9V, Id=2nA (2mV across 1M)
(all voltages negative. Datasheet specs use Vds=15V)

3.56, 3.34, 1.90, 3.46, 2.44, 3.69, 3.97, 3.21, 3.58,
3.44, 2.20, 2.96, 2.39, 4.65, 3.47, 4.06, 3.28, 4.02,
3.76, 2.62, 1.92, 2.85, 3.05, 3.14, 3.55, 2.10**

**The 2.10V is the JFET I have been using for the oscillator.

As you can see, altho there was a somewhat wide variation, most of them
were in the 2 to 4V range.

With Vgs(off) in this range, your FETs should have transconductances much higher than

the 2000 minimum. I just can't understand the behavior you're getting (oscillations dying
out). I may have to see if I can find an MPF102 of my own and breadboard this thing.

I hope you can try the fixed source bias idea; I think we could get some good info from
that.

 

[The Phantom]

On Sat, 8 Jan 2005 19:26:03 -0800, "Watson A.Name - \"Watt Sun, the
Dark Remover\"" <NOSPAM@dslextreme.com> wrote:

Anyway, I think the variable bias supply and no capacitor would be
a good experiment to
try.

Well, I still have to bypass the bias supply,

You bypassed it with 3200uF before; at .67Hz that's an impedance of
74 ohms. Why do a lot better than that now? If you put a 100 ohm
trimpot across your bias supply with the wiper connected to the source
as I proposed, you would have a maximum of 25 ohms source resistance
(with the trimpot set in the middle; less at any other setting)
without any capacitor, which I think would be a good thing; (the lack
of a capacitor, that is . Getting rid of the capacitor also
eliminates the complication of extra phase shift that John Jardine
discussed.

so it'll have almost no
degeneration on the oscillations. I changed from a zener to TL430, and
some pot that will handle a bit of current. I have to get the TL430 in
there somewhere. I'm working on it.

;-) Thanks.

[snip]

 

[Tony Williams]

In article <bj65u0prck12kkb1i4dliaf4a1knnh0r5p@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:

Come on, Tony, you done gone and ruined this whole thread by
introducing some actual engineering thought into the process ;-)

Sorry Jim.......

The folded cascode (with dc feedback bias) was my favorite
circuit when using a single jfet, it evades all sorts of
problems. By ratio'ing the currents it is even possible
to do the self-bias for constant gm, as per the Siliconix
app note TA70-2.

In this case, getting 29x off a 9Vdc rail is possible,
but still a little too marginal for comfort.

--
Tony Williams.