low-level vs. high-level

[Evgeny Filatov]

On 14.09.2015 1:53, glen herrmannsfeldt wrote:

Evgeny Filatov <e.v.filatov@ieee.org> wrote:

(snip, I wrote)

I do remember using schematic drawing tools, but most often found
it took a lot of work drawing lines, making sure that they didn't
overlap what they weren't supposed to, and otherwise getting it right.

But I can write some lines of verilog or VHDL and not have to worry
about such lines overlapping. Match up signal names and everything
works the way it is supposed to.

(snip)

Tim is correct. An example (GPS C/A stuff):

http://tinyurl.com/nfmqjzm

I just suck at writing in VHDL/verilog. Should practice more.

OK, the tools are surprisingly good at doing what needs to be done.

If the problem is well described at the higher level, it is probably
fine.

If you need the highest speed, though, you might need to pipeline it,
and that might not be so easy from the high level representation.

If it is fast enough, and the high-level logic mostly does what
you want, you might not need to worry.

-- glen

Thanks for the feedback, Glen, Rick, BobH and everyone else. I think
I've understood that while it's no crime to use schematic tools, writing
in VHDL/verilog offers greater flexibility and thus potential advantages
in performance.

Regards,
Evgeny.

 

[Jon Elson]

rickman wrote:

I just suck at writing in VHDL/verilog. Should practice more.

Certainly VHDL can be verbose and it can present stumbling blocks to a
newbie. I came from a world of schematics, so it isn't hard to impress
me considering the huge improvement in productivity.

I dug myself a BIG hole about a decade ago, and I'm still recovering from
the experience.

I got into small-scale programmable hardware design with Xilinx CPLDs (9500
series) and used schematics, because these were really not typical designs.
The first 9500 design was basically using the chips as a way to get hundreds
of FFs, all with different clock sources in a small area. ONLY Xilinx could
do this, other makers required all the FFs to be clocked from global clock
lines. So, the 9500 was the perfect device for this very odd requirement.

But, then, I realized the benefits of the CPLD and FPGA devices, and started
using the Xilinx Foundation tools to enter schematics. I built the projects
out of 8-bit FDC's, 8-bit tri-states and such components familiar to the
74xx logic designer.

But, I hated the Aldec schematic tool in Foundation, and discovered my
beloved Protel 99SE could make really NICE schematics, at about 4X the
density of the Aldec ones, without the frustrating auto-line creation that
drove me nuts! But, the Protel-created VHDL was not perfectly acceptable to
Xilinx, I had to edit a few little bits in the files. So, then, instead of
making all changes to the schematics, I started editing the computer-
generated structural VHDL, which were VERY hard for a human to read.
Hundreds of instances of inverters, gates and FFs, with lots of NetU107_O3
auto-generated net names and such.

Slowly, over time, when a major change to one of these horrors was needed, I
would completely recode it into behavioral VHDL, which was far more
comprehensible, not to mention reducing 10+ pages of stuff to just a little
more than one page!

I still use structural VHDL for the top module, but now realize the huge
error I made in doing all the schematics. Of course, part of the mistake
was using a tool that "almost" worked. Also, Protel attempted to clone the
schematic library parts from the Xilinx vcomp library, and apparently
trained a secretary to enter all of them. I think they forgot to tell her
those dots where lines crossed had any special meaning! So, I had to go in
and correct about 50 of the library components, and then keep track of which
ones had been fixed. Then, recently, I moved the hand-edited structural
stuff to ise 13.4, and had CRAZY problems. I finally traced it to the
definition of which inputs of partial-DeMorgan NOR gates were the inverted
ones. I think on Ise 10, a NOR2B1 had the SECOND input inverted, on 13.4
the FIRST input is now the inverted one. Took a LONG time to guess that was
what was going wrong. I ripped out all the deMorgan-type gates and placed
explicit inverters.

Well, I LEARNED something from the experience! (I hope!)

Jon

 

[Anssi Saari]

BobH <wanderingmetalhead.nospam.please@yahoo.com> writes:

If you are using a good optimizing synthesis tool chain, the
difference may not be very large. I used some Mathcad generated RTL on
a project, and by the time the synthesis tool was done, it was as
tight as I could have gotten it by hand.

Does Mathcad really have RTL generation these days? Or did you mean
Matlab?

 

[BobH]

On 9/18/2015 2:14 AM, Anssi Saari wrote:

BobH <wanderingmetalhead.nospam.please@yahoo.com> writes:

If you are using a good optimizing synthesis tool chain, the
difference may not be very large. I used some Mathcad generated RTL on
a project, and by the time the synthesis tool was done, it was as
tight as I could have gotten it by hand.

Does Mathcad really have RTL generation these days? Or did you mean
Matlab?

You are correct, it is Matlab. I don't use either much anymore and
always mix them up.