Looking for VHDL consult.

[KR Williams]

In article <c8gpfp02069@news3.newsguy.com>,
crcarle@BOGUS.sandia.gov says...

Ken Smith wrote:
In article <c8ge8401doa@news3.newsguy.com>,
Chris Carlen <crcarle@BOGUS.sandia.gov> wrote:
[...]

The point of my question was that I'd consider an HDL to be as low-level
as one can get, considering it's used to describe the hardware that
comes before even the assembler language can run on anything.


Take a look at CUPL, PALASM and ABEL to see a lower level language. In
those you actually get to talk about flop-flops and macro cells etc. I
expect that if I was using PALASM I'd be done by now.


I almost considered ABEL, until the folks at comp.arch.fpga convinced me
to go with one of VHDL or Verilog. But I'd agree it's about the lowest
level, along with the others you mentioned.

If you want low level, VHDL can instantiate gates and FFs, as
well. You can even instantiate the placement information.
However, this throws any portability (even across like devices)
out the window.

I don't hesitate to use gate level and structural modeling in Verilog,
which is quite appropriate for relatively small logic designs like much
of what I do. It's still easier to edit and modify than a graphic
schematic diagram. Though schematics are nicer to read sometimes.

The nice thing about HDL over schematics is that they can be
edited on any text editor. What guarantee is there that the
schematic entry tool will work next year. Though I prefer
schematics for data-flow and VHDL for FSMs. Of course there are
also schematic entry tools that will output VHDL (and I suppose
Verilog) so one can live in both worlds.

--
Keith

 

[KR Williams]

In article <c8g4cp$aqs$2@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <c8e9f9112q9@news3.newsguy.com>,
Chris Carlen <crcarle@BOGUS.sandia.gov> wrote:
[...]
High level language? Higher than what

The "high level language" term is a marketing term. It has no real
meaning. It is very like the "forth generation language" term that was so
common a few years ago. It is how stuff gets sold to managers.

Basically they rank them like this:

Assembler
Basic
C
C++
ADA
Spreadsheets

I'd put C right next to assembler. After all, C is just a set of
assembler macros. ;-)

--
Keith

 

[Rich Grise]

"KR Williams" <krw@att.biz> wrote in message
news:MPG.1b19439da5e4f8719898da@news1.news.adelphia.net...

In article <c8g4n1$aqs$3@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <38ela01a78gpc4bfpsjj7ujef64nmipquc@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:
[... VHDL ...]
High level language? Higher than what?

As in (Digital) Descriptive Languages.
VHDL = (V)ery (H)ard (D)escriptive (L)anguage
VHDL == VLSI Hardware Description Language
or should that be "High"?
Some people think the developers were. ;-)

I thought VHDL == Very High Density Logic.

Go figure.
Rich

 

[KR Williams]

In article <twesc.7326$o97.5282@nwrddc01.gnilink.net>,
null@example.net says...

"KR Williams" <krw@att.biz> wrote in message
news:MPG.1b19439da5e4f8719898da@news1.news.adelphia.net...
In article <c8g4n1$aqs$3@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <38ela01a78gpc4bfpsjj7ujef64nmipquc@4ax.com>,
Jim Thompson <thegreatone@example.com> wrote:
[... VHDL ...]
High level language? Higher than what?

As in (Digital) Descriptive Languages.
VHDL = (V)ery (H)ard (D)escriptive (L)anguage
VHDL == VLSI Hardware Description Language
or should that be "High"?
Some people think the developers were. ;-)

I thought VHDL == Very High Density Logic.

Actually, I misremembered it. VHDL == VHSIC Hardware Description
Language, where VHSIC == Very High Speed Integrated Circuit.

I got to thinking that "V==VLSI" was too simple. ;-)

--
Keith

 

[Ken Smith]

In article <MPG.1b194628322e8c99898dd@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]

If you want low level, VHDL can instantiate gates and FFs, as
well.

Yes but as I (mis)understand the rules of VHDL, that flip-flop may or may
not represent the actual flip-flop created in the resulting device. You
are allowed to specify a T-flip-flop on a part that doesn't have one. The
fitter will create one out of several parts if needed. In things like
PALASM, if the chip doesn't have a T-flip-flop mode in the macrocell, you
cant specify one in the design. I believe Abel does convert between
flip-flop types though.

--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <MPG.1b19439da5e4f8719898da@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]

It depends on how the code is written. If the appropriate
libraries are used the code can be very portable (just like C).

From my experience with Cypress's Warp and Altera's Quartus, there is no
way to make a design portable.

In Warp X <= 'Z'; makes a tri-state. In Quartus, it makes an error.

If the target hardware (or processor) doesn't have equivalent
functions (instructions) it won't be portable.

The Altera Max series and the Cypress Ultra series both have about the
same stuff inside.


--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <MPG.1b1bb4b9860cd2719898fa@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:

kensmith@violet.rahul.net says...
VHDL = (V)ery (H)ard (D)escriptive (L)anguage

Actually, I misremembered it. VHDL == VHSIC Hardware Description
Language, where VHSIC == Very High Speed Integrated Circuit.

I still like mine better!

--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <MPG.1b19466ceaaec6aa9898de@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:

In article <c8g4cp$aqs$2@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <c8e9f9112q9@news3.newsguy.com>,
Chris Carlen <crcarle@BOGUS.sandia.gov> wrote:
[...]
High level language? Higher than what

The "high level language" term is a marketing term. It has no real
meaning. It is very like the "forth generation language" term that was so
common a few years ago. It is how stuff gets sold to managers.

Basically they rank them like this:

Assembler
Basic
C
C++
ADA
Spreadsheets

I'd put C right next to assembler. After all, C is just a set of
assembler macros. ;-)

All but the spreadsheet are right next to Assembler. A Compiler puts
things together as does an Assembler.

If you want to get far from assembler, you should look at APL. You can
write a complete tic-tac-toe game in 4 lines of APL. You can distribute
the source code without fear of anyone else understanding it too so it is
great for security applications. :>


--
--
kensmith@rahul.net forging knowledge

 

[KR Williams]

In article <c8t8qo$p1a$1@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <MPG.1b194628322e8c99898dd@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
If you want low level, VHDL can instantiate gates and FFs, as
well.

Yes but as I (mis)understand the rules of VHDL, that flip-flop may or may
not represent the actual flip-flop created in the resulting device. You
are allowed to specify a T-flip-flop on a part that doesn't have one. The
fitter will create one out of several parts if needed. In things like
PALASM, if the chip doesn't have a T-flip-flop mode in the macrocell, you
cant specify one in the design. I believe Abel does convert between
flip-flop types though.

A VHDL (or Verilog) design can be done either way. One can
directly instantiate a TFF from the given library, or describe
its function. If one instantiates the TFF and it doesn't exist
the design won't compile, since the library element called
doesn't exist. If one describes the function of a box, then it
will be built out of what is available (if possible).

Obviously if one instantiates the primitives one is locked into a
technology with those primitives available. If one writes at a
higher level, one is at the mercy of the compiler to generate a
good design. I generally end up doing both, but separate the
code into very distinct modules. If I do need to port the design
at least I know what's funky.

VHDL also allows functions that cannot be realized in logic
(delay blocks, for instance). While these cannot generate
hardware, they are useful for test benches.

--
Keith

 

[KR Williams]

In article <c8t92j$p1a$2@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <MPG.1b19439da5e4f8719898da@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
It depends on how the code is written. If the appropriate
libraries are used the code can be very portable (just like C).

From my experience with Cypress's Warp and Altera's Quartus, there is no
way to make a design portable.

In Warp X <= 'Z'; makes a tri-state. In Quartus, it makes an error.

This is a legal VHDL statement and should compile correctly, at
least if there is such a thing as tristate. Even if there isn't
the compiler should build mux's out of the tristates. A tristate
driver is described by:

MyOutput <= MyInput when MyEnable = '0' otherwise 'Z';

The compiler should do what it needs to do to build the necessary
logic. Even in technologies without tristates the proper logic
should be built. At least Synplify would build either tri-state
drivers (if available) or mux's depending on compiler directives.

If the target hardware (or processor) doesn't have equivalent
functions (instructions) it won't be portable.

The Altera Max series and the Cypress Ultra series both have about the
same stuff inside.

Are the libraries the same? If the libraries have elements with
the same names (unlikely), then directly instantiated designs
will be portable. If the logic is described (rather than using
instantiated library elements) then the compiler will fit the
design to the libraries available to it.

--
Keith

 

[KR Williams]

In article <c8t9gl$p1a$4@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <MPG.1b19466ceaaec6aa9898de@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
In article <c8g4cp$aqs$2@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <c8e9f9112q9@news3.newsguy.com>,
Chris Carlen <crcarle@BOGUS.sandia.gov> wrote:
[...]
High level language? Higher than what

The "high level language" term is a marketing term. It has no real
meaning. It is very like the "forth generation language" term that was so
common a few years ago. It is how stuff gets sold to managers.

Basically they rank them like this:

Assembler
Basic
C
C++
ADA
Spreadsheets

I'd put C right next to assembler. After all, C is just a set of
assembler macros. ;-)

All but the spreadsheet are right next to Assembler. A Compiler puts
things together as does an Assembler.

Think indirection. An assembler produces one machine instruction
for every source instruction. A macro assembler expands a single
directive into many machine instructions. A compiler doesn't
have a direct 1:1 correlation between language statements and
machine instructions.

If you want to get far from assembler, you should look at APL. You can
write a complete tic-tac-toe game in 4 lines of APL. You can distribute
the source code without fear of anyone else understanding it too so it is
great for security applications. :

APL is well known to be a write-only language. It's an
engineer's language and anything written in it should be treated
as throw-away code. I'd be surprised if it couldn't be written
in one, BTW.

 

[Ken Smith]

In article <MPG.1b1c109a8270ba449898fb@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:

In article <c8t8qo$p1a$1@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <MPG.1b194628322e8c99898dd@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
If you want low level, VHDL can instantiate gates and FFs, as
well.

PALASM, if the chip doesn't have a T-flip-flop mode in the macrocell, you
cant specify one in the design. I believe Abel does convert between
flip-flop types though.

A VHDL (or Verilog) design can be done either way. One can
directly instantiate a TFF from the given library, or describe
its function. If one instantiates the TFF and it doesn't exist
the design won't compile, since the library element called
doesn't exist. If one describes the function of a box, then it
will be built out of what is available (if possible).

I think you misunderstood my point.

In VHDL you can have a thing called a TFF in a library and you project
will compile even if the TFF had to be composed by the fitter. In PALASM
if the chip its self doesn't implement a type of flip-flop, you can't use
that sort of flip-flop in your design. (See below)

Obviously if one instantiates the primitives one is locked into a
technology with those primitives available.

This isn't really true. You can create a library, of your own, that
explains the function of that primative in VHDL and then you can compile
your design. I could write the VHDL to make a library with a TFF in it
that did the same thing as the TFF in some other library. If I then used
my library, it would complile in my version of the TFF. My version would
free me from the dependance on the hardware.



--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <MPG.1b1c12e664810e9e9898fc@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:

In article <c8t92j$p1a$2@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <MPG.1b19439da5e4f8719898da@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
It depends on how the code is written. If the appropriate
libraries are used the code can be very portable (just like C).

From my experience with Cypress's Warp and Altera's Quartus, there is no
way to make a design portable.

In Warp X <= 'Z'; makes a tri-state. In Quartus, it makes an error.

This is a legal VHDL statement

Yes I thought it was.

and should compile correctly,

Its that word "should" that causes me so much trouble. It should compile
to a tri-state output since the X in question is a pin of the chip.

The compiler should do what it needs to do to build the necessary
logic.

There's that dang word "should" again.

Even in technologies without tristates the proper logic
should be built.

Not in my case because the tri-state in question was a pin of the chip.
The VHDL can't reach out and change the micro's data bus into 2 busses
(one for each direction). As a result I really needed the tri-state.

The Altera Max series and the Cypress Ultra series both have about the
same stuff inside.

Are the libraries the same?

Not really. I don't even think the Cypress has the TRI() component in it.
This is Altera's answer to doing a tristate connection.

[...]

If the logic is described (rather than using
instantiated library elements) then the compiler will fit the
design to the libraries available to it.

I am doing it all in logic. The components I'm using are all defined as
chunks of logic.

BTW: You should have said "the compiler *should* fit". Altera admits to
the bug involving the tri-state.

--
--
kensmith@rahul.net forging knowledge

 

[Ken Smith]

In article <MPG.1b1c14091a48bd6e9898fd@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]

Think indirection. An assembler produces one machine instruction
for every source instruction.

Except for the funny "prefix" action of the 80X86 assemblers. With them
you get less than one instruction per line if you say a prefix is part of
an instruction. If you call a prefix an instruction, then you can get
more than one per line.

Actually with Intels assembler, all instructions were macros of sorts.
You could add instructions to the assembler without recompiling.

[..tic-tac-toe in APL ..]

APL is well known to be a write-only language.

Actually I found I could read it. You just have to read very slowly from
the right to the left to read statements and left to right to read
comments. The back and forth takes a bit of getting used to.

[...]

I'd be surprised if it couldn't be written
in one, BTW.
The rules of the game were such that bogus constructs to allow continued

lines were not allowed. No "comma zero rho" type statement extenders
where allowed. As a result, I think 4 lines in about the minimum.



--
--
kensmith@rahul.net forging knowledge

 

[KR Williams]

In article <c8tqm4$vgn$2@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <MPG.1b1c12e664810e9e9898fc@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
In article <c8t92j$p1a$2@blue.rahul.net>,
kensmith@violet.rahul.net says...
In article <MPG.1b19439da5e4f8719898da@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
It depends on how the code is written. If the appropriate
libraries are used the code can be very portable (just like C).

From my experience with Cypress's Warp and Altera's Quartus, there is no
way to make a design portable.

In Warp X <= 'Z'; makes a tri-state. In Quartus, it makes an error.

This is a legal VHDL statement

Yes I thought it was.

It may be legal, but not real. If you've assigned a 'Z' to a
signal that already has another value, *you're* wrong, and the
compiler is telling you this. Anytime you assign a 'Z' to a
signal, it cannot ever have another state, You've told the
compiler this.

and should compile correctly,

Its that word "should" that causes me so much trouble. It should compile
to a tri-state output since the X in question is a pin of the chip.

As long as you want that pint to be forever a 'Z' there should be
no problem. I doubt that's what you want though.

The compiler should do what it needs to do to build the necessary
logic.

There's that dang word "should" again.

Look inward with that "should". You're the one causing the
compiler to go nutzo, me thinks.

Even in technologies without tristates the proper logic
should be built.

Not in my case because the tri-state in question was a pin of the chip.

Let me guess, you're a programmer and don't understand
concurrancy. You're defining a port as a 'Z', but something else
is defining it otherwise. Typical programmer mentality.

The VHDL can't reach out and change the micro's data bus into 2 busses
(one for each direction). As a result I really needed the tri-state.

I told you how to do this. Stop thinking like a dumb programmer.
VHDL is *concurrent*, not linear. Dumb programmers think linear.
;-)

The Altera Max series and the Cypress Ultra series both have about the
same stuff inside.

Are the libraries the same?

Not really. I don't even think the Cypress has the TRI() component in it.
This is Altera's answer to doing a tristate connection.

Exactly. You're dead-set in your programmer mentality. HDLs are
different because hardware is *parallel*, not sequential, as you
seem to think.

If the logic is described (rather than using
instantiated library elements) then the compiler will fit the
design to the libraries available to it.

I am doing it all in logic. The components I'm using are all defined as
chunks of logic.

Give us an example. My bet is that you aren't doing what you
think you are.

BTW: You should have said "the compiler *should* fit". Altera admits to
the bug involving the tri-state.

Whatever. If Altera has admitted their issue, so be it. I still
think you're thinking too sequentially. Hardware doesn't act
sequentially, so the description languages don't either.
(evidence; assigning 'Z' to a signal will forever make it a 'Z',
though that's likely not what you wanted).

--
Keith

 

[KR Williams]

In article <c8tr72$vgn$3@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <MPG.1b1c14091a48bd6e9898fd@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
Think indirection. An assembler produces one machine instruction
for every source instruction.

Except for the funny "prefix" action of the 80X86 assemblers. With them
you get less than one instruction per line if you say a prefix is part of
an instruction. If you call a prefix an instruction, then you can get
more than one per line.

Oh, my. We are being pedantic, eh? Instructions are specified
in the ISA. If the instructions = ISA then it's an assembler.

Actually with Intels assembler, all instructions were macros of sorts.
You could add instructions to the assembler without recompiling.

....and this would produce what?

APL is well known to be a write-only language.

Actually I found I could read it. You just have to read very slowly from
the right to the left to read statements and left to right to read
comments. The back and forth takes a bit of getting used to.

You are just sooo special! Noone else could, including the few
tens of engineers I knew who were specialists. It is a read-only
language.

I'd be surprised if it couldn't be written
in one, BTW.

The rules of the game were such that bogus constructs to allow continued
lines were not allowed. No "comma zero rho" type statement extenders
where allowed. As a result, I think 4 lines in about the minimum.

Ah, now you're throwing more artificial rules into the mix (as
above with your definition of a "compiler"). Make yourself
happy!

--
Keith

 

[Ken Smith]

In article <MPG.1b1c723bf46d993a9898ff@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
I wrote:

In Warp X <= 'Z'; makes a tri-state. In Quartus, it makes an error.

This is a legal VHDL statement

Yes I thought it was.

It may be legal, but not real. If you've assigned a 'Z' to a
signal that already has another value, *you're* wrong, and the
compiler is telling you this. Anytime you assign a 'Z' to a
signal, it cannot ever have another state, You've told the
compiler this.

Actually the Z <= 'Z' is part of a process. It is in one condition of an
"If" statement. The other assigns a value to the pin.

[....]

Look inward with that "should". You're the one causing the
compiler to go nutzo, me thinks.

The whole subject of this thead was about me looking for someone who is a
VHDL expert to help out on this project. I'm not completely opposed to
the idea that I'm causing the problem. Exactly why the Cypress compiler
produced a result that is ok and the Altera didn't is a bit of a question.
It could be that the Cypress program doesn't correctly trap some error in
the VHDL.

[...]

Let me guess, you're a programmer and don't understand
concurrancy. You're defining a port as a 'Z', but something else
is defining it otherwise. Typical programmer mentality.

I won't take that as an insult. I do understand concurrancy quite well an
have coded many PALs and CPLDs over the years. This is the first time
I've used VHDL


[...]
Changing the bus of a Micro.

I told you how to do this. Stop thinking like a dumb programmer.
VHDL is *concurrent*, not linear. Dumb programmers think linear.
;-)

Yeah right. This CPLD is connected to a pair of high performance micros
and a fast RAM and some other stuff. The Micros and the RAM have
bidirectional data busses. I have to tri-state the CPLD's pins if they
are connected to the data busses. There is no option.



[...]

Exactly.
You're dead-set in your programmer mentality.

That is insulting. Good bye


--
--
kensmith@rahul.net forging knowledge

 

[KR Williams]

In article <c8vl56$snh$1@blue.rahul.net>,
kensmith@violet.rahul.net says...

In article <MPG.1b1c723bf46d993a9898ff@news1.news.adelphia.net>,
KR Williams <krw@att.biz> wrote:
[...]
I wrote:
In Warp X <= 'Z'; makes a tri-state. In Quartus, it makes an error.

This is a legal VHDL statement

Yes I thought it was.

It may be legal, but not real. If you've assigned a 'Z' to a
signal that already has another value, *you're* wrong, and the
compiler is telling you this. Anytime you assign a 'Z' to a
signal, it cannot ever have another state, You've told the
compiler this.

Actually the Z <= 'Z' is part of a process. It is in one condition of an
"If" statement. The other assigns a value to the pin.

That's information not before supplied.

Look inward with that "should". You're the one causing the
compiler to go nutzo, me thinks.

The whole subject of this thead was about me looking for someone who is a
VHDL expert to help out on this project. I'm not completely opposed to
the idea that I'm causing the problem. Exactly why the Cypress compiler
produced a result that is ok and the Altera didn't is a bit of a question.
It could be that the Cypress program doesn't correctly trap some error in
the VHDL.

This isn't a consultant-for-hire group. There are designers here
who might be able to solve your problems, if they're stated.
Without more of a testcase (code snippet) it's impossible to tell
what the issue is. Perhaps your code is too complicated for the
Altera tools. Without more information it's hard to tell.

Let me guess, you're a programmer and don't understand
concurrancy. You're defining a port as a 'Z', but something else
is defining it otherwise. Typical programmer mentality.

I won't take that as an insult. I do understand concurrancy quite well an
have coded many PALs and CPLDs over the years. This is the first time
I've used VHDL

Your error, and information provided, pointed me to a concurrancy
problem. Assigning a value to a signal in two places is a common
error.

[...]
Changing the bus of a Micro.

I told you how to do this. Stop thinking like a dumb programmer.
VHDL is *concurrent*, not linear. Dumb programmers think linear.
;-)


Yeah right. This CPLD is connected to a pair of high performance micros
and a fast RAM and some other stuff. The Micros and the RAM have
bidirectional data busses. I have to tri-state the CPLD's pins if they
are connected to the data busses. There is no option.

I didn't say that tri-state wasn't correct, but you've likely got

something in your code that's conflicting. ....or perhaps the
compiler things it *could*.

[...]
Exactly.
You're dead-set in your programmer mentality.

That is insulting. Good bye

Perhaps I assumed too much, but that's where your statements were
leading me. Perhaps you should state the *whole* problem.
Better yet, comp.arch.vhdl is likely the best place to get an
answer to a problem like this.

--
Keith

 

[Allan Herriman]

On Tue, 25 May 2004 11:37:59 -0400, KR Williams <krw@att.biz> wrote:

Better yet, comp.arch.vhdl is likely the best place to get an
answer to a problem like this.

Try comp.arch.fpga as well.

Regards,
Allan.

 

[KR Williams]

In article <MPG.1b1d324c7b0f45989905@news1.news.adelphia.net>,
krw@att.biz says...

Better yet, comp.arch.vhdl is likely the best place to get an
answer to a problem like this.

Make that comp.lang.vhdl.

--
Keith