looking for TTL latch IC

[exxos]

Hi all,

I'm trying to find a 4bit Latch with input enable, NOT output enable. Theres
many chips which will disable the outputs though I want the data to latch,
and then via a enable pin disconnect the inputs , but leave the data on the
outputs latched.

At the mement im having to use a seperate 3 state buffer to isolate the
inputs, but there must be a latch IC out there with input enable ??

thanks
chris

 

[Peter Bennett]

On Wed, 19 May 2004 19:33:05 +0100, "exxos" <exxos@home.co.uk> wrote:

Hi all,

I'm trying to find a 4bit Latch with input enable, NOT output enable. Theres
many chips which will disable the outputs though I want the data to latch,
and then via a enable pin disconnect the inputs , but leave the data on the
outputs latched.

At the mement im having to use a seperate 3 state buffer to isolate the
inputs, but there must be a latch IC out there with input enable ??

thanks
chris

How does your proposed Input Enable differ from the normal latch
enable/clock? A latch does not look at its inputs except when its
latch/enable input is high (in the case of the 7475 and similar
parts), and it holds the previous state of its inputs when the enable
goes low. If you have a separate signal to disconnect the inputs,
what value do the latches store when the enable goes low, if the
inputs are disconnected?




--
Peter Bennett, VE7CEI
peterbb4 (at) interchange.ubc.ca
new newsgroup users info : http://vancouver-webpages.com/nnq
GPS and NMEA info: http://vancouver-webpages.com/peter
Vancouver Power Squadron: http://vancouver.powersquadron.ca

 

[Michael Black]

"exxos" (exxos@home.co.uk) writes:

Hi all,

I'm trying to find a 4bit Latch with input enable, NOT output enable. Theres
many chips which will disable the outputs though I want the data to latch,
and then via a enable pin disconnect the inputs , but leave the data on the
outputs latched.

At the mement im having to use a seperate 3 state buffer to isolate the
inputs, but there must be a latch IC out there with input enable ??

thanks
chris


This doesn't make sense.

A latch, by its very definition, will grab whatever's on the input
and latch it when you toggle the latch pin properly. There's no reason
to detach the input, because its load will be minimal, and the input
will not mirror to the output unless you have the latch pin set (and
even then, it depends on the particular latch).

There isn't much in the way of a 4-bit latch, except the 7475 (or
variants) and I don't even know if it's still available. The "enable"
pin is normally low, and the output does not vary. Hold the "enable"
pin high, and anything at the input will appear at the output. But if
you just pulse the "enable" pin, whatever is at the input at the time
of this pulse will be latched, and seen at the output until you
clock the "enable" pin again.

The 7475 is four type D flip flops in a package, so you could
duplicate it with two dual type D flip flops if you were stuck.

For a long time, the standard has been 8bits, which tend to
be more useful than a 4bit latch, especially since you can always
ignore the extra bits if needed. There are various iterations,
likely including at least one that does not have tri-state logic.
If you don't need tri-state output, it doesn't matter because
you can simply leave the output enabled.

The 74373 works like the 7475, except it has 8bits. The 74374
is edge triggered, meaning that the latch will grab what's at
the input as the "enable" (it actually is referred to as "enable"
with the 7475) or "clock" pin goes high. It will not follow
the input data while that pin is high, unlike the 7475 and the 74374.

I'm not sure your question is quite clear. You might want to give
an example of what you are doing.

Michael

 

[R. Steve Walz]

exxos wrote:

Hi all,

I'm trying to find a 4bit Latch with input enable, NOT output enable. Theres
many chips which will disable the outputs though I want the data to latch,
and then via a enable pin disconnect the inputs , but leave the data on the
outputs latched.

At the mement im having to use a seperate 3 state buffer to isolate the
inputs, but there must be a latch IC out there with input enable ??

thanks
chris
--------------------------------

What you're talking about without knowing it, is a transparent latch.
The only ones like that in TTL are the '373 and '573. They also have
tri-state outputs. The control pins are LE, latch enable (active HI)
and /OE output enable, (active LO). The latch enable enables data in
to become the output state instantly, and the last data state to
remain the output state once it goes LO and for as long as it does,
and the output only be changed if the LE goes HI AND the data is
different than the last latched output state.

There are no TTL transparent latches except those two chips.

-Steve
--
-Steve Walz rstevew@armory.com ftp://ftp.armory.com/pub/user/rstevew
Electronics Site!! 1000's of Files and Dirs!! With Schematics Galore!!
http://www.armory.com/~rstevew or http://www.armory.com/~rstevew/Public

 

[R. Steve Walz]

R. Steve Walz wrote:

exxos wrote:

Hi all,

I'm trying to find a 4bit Latch with input enable, NOT output enable. Theres
many chips which will disable the outputs though I want the data to latch,
and then via a enable pin disconnect the inputs , but leave the data on the
outputs latched.

At the mement im having to use a seperate 3 state buffer to isolate the
inputs, but there must be a latch IC out there with input enable ??

thanks
chris
--------------------------------
What you're talking about without knowing it, is a transparent latch.
The only ones like that in TTL are the '373 and '573. They also have
tri-state outputs. The control pins are LE, latch enable (active HI)
and /OE output enable, (active LO). The latch enable enables data in
to become the output state instantly, and the last data state to
remain the output state once it goes LO and for as long as it does,
and the output only be changed if the LE goes HI AND the data is
different than the last latched output state.

There are no TTL transparent latches except those two chips.

-Steve
--

Oops, oh yeah, I just checked, the 7475 quad (4-bit) latch is also
transparent, but has no tristate (no /OE) capability.

-Steve
--
-Steve Walz rstevew@armory.com ftp://ftp.armory.com/pub/user/rstevew
Electronics Site!! 1000's of Files and Dirs!! With Schematics Galore!!
http://www.armory.com/~rstevew or http://www.armory.com/~rstevew/Public

 

[exxos]

"Michael Black" <et472@FreeNet.Carleton.CA> wrote in message
news:c8haqr$76v$1@freenet9.carleton.ca...

"exxos" (exxos@home.co.uk) writes:
Hi all,

I'm trying to find a 4bit Latch with input enable, NOT output enable.
Theres
many chips which will disable the outputs though I want the data to
latch,
and then via a enable pin disconnect the inputs , but leave the data on
the
outputs latched.

At the mement im having to use a seperate 3 state buffer to isolate the
inputs, but there must be a latch IC out there with input enable ??

thanks
chris


This doesn't make sense.

A latch, by its very definition, will grab whatever's on the input
and latch it when you toggle the latch pin properly. There's no reason
to detach the input, because its load will be minimal, and the input
will not mirror to the output unless you have the latch pin set (and
even then, it depends on the particular latch).

There isn't much in the way of a 4-bit latch, except the 7475 (or
variants) and I don't even know if it's still available. The "enable"
pin is normally low, and the output does not vary. Hold the "enable"
pin high, and anything at the input will appear at the output. But if
you just pulse the "enable" pin, whatever is at the input at the time
of this pulse will be latched, and seen at the output until you
clock the "enable" pin again.

The 7475 is four type D flip flops in a package, so you could
duplicate it with two dual type D flip flops if you were stuck.

For a long time, the standard has been 8bits, which tend to
be more useful than a 4bit latch, especially since you can always
ignore the extra bits if needed. There are various iterations,
likely including at least one that does not have tri-state logic.
If you don't need tri-state output, it doesn't matter because
you can simply leave the output enabled.

The 74373 works like the 7475, except it has 8bits. The 74374
is edge triggered, meaning that the latch will grab what's at
the input as the "enable" (it actually is referred to as "enable"
with the 7475) or "clock" pin goes high. It will not follow
the input data while that pin is high, unlike the 7475 and the 74374.

I'm not sure your question is quite clear. You might want to give
an example of what you are doing.

Michael

I think I was getting confused with enable and tri-state. I was thinking
when then IC is disabled the outputs will be turned off. What I am looking
is monitor 4 data lines, when one goes high, it will latch on, but at the
same time the 4 latch outputs are ORed back into the enable pin, so any
further inputs will be ignored by the latch. I think the 373 will do what is
needed.

thanks
chris

 

[John Fields]

On Thu, 20 May 2004 16:51:57 +0100, "exxos" <exxos@home.co.uk> wrote:

I think I was getting confused with enable and tri-state. I was thinking
when then IC is disabled the outputs will be turned off. What I am looking
is monitor 4 data lines, when one goes high, it will latch on, but at the
same time the 4 latch outputs are ORed back into the enable pin, so any
further inputs will be ignored by the latch. I think the 373 will do what is
needed.

---
That doesn't make any sense.

Why don't you tell us what you're trying to do instead of how you
think you want to do it?

--
John Fields

 

[exxos]

"John Fields" <jfields@austininstruments.com> wrote in message
news:eiopa0pvv22f0tens4t6vdthuie9cl62ck@4ax.com...

On Thu, 20 May 2004 16:51:57 +0100, "exxos" <exxos@home.co.uk> wrote:


I think I was getting confused with enable and tri-state. I was thinking
when then IC is disabled the outputs will be turned off. What I am
looking
is monitor 4 data lines, when one goes high, it will latch on, but at the
same time the 4 latch outputs are ORed back into the enable pin, so any
further inputs will be ignored by the latch. I think the 373 will do what
is
needed.

---
That doesn't make any sense.

Why don't you tell us what you're trying to do instead of how you
think you want to do it?

--
John Fields

What I have at the moment which works fine, is a 3state buffer, 74HC541, and
4 2N5060 thyristors, when the 541 has a input it goes right though the
buffer.... the buffer then triggers the thyristor which latches on and stays
on. The voltages on the thyristor are also feed back into the 3state buffer
turning it off. Now should a input to the buffer rise again, nothing will
happen, and no latching will happen since the thyristors are isolated from
the input lines via the 541 buffer. This all works fine.......

Now what I want to do is do the same thing but with 1 IC, A latch IC. Now I
want the same to happen but without using seperate devices. I want to latch
a input line (like my thyristors does), then once one of the 4 latches are
on, I then want to isoltate the latches from the incomming inputs (like me
3state buffer does).

In anycase, the outputs of the buffer are going via a 4input OR gate and
then going to the 3state pin on the buffer. So when any input goes high,
that input is latched on and the buffer is disabled from any further inputs.

What I am not sure of is the 373 latch. If I have a input, normally to latch
it you have to pulse the clock pin to clock it into the latch. Normally
AFAIK if the clock pin stays high whatever is on the inputs appears on the
ouputs , and latched when the clock line goes low. (this is what the 374
looks to do).

I am not sure how the data and enable are working on the 373. I assume while
LE is high any data will be latched. Though the datasheet seems unclear if
its actually latched, or the outputs are just following the inputs (as it
would while the clock on the 374 were high).

I assume that on the 373 while LE is high, the data is latched, which looks
to me asif the outputs are just following the inputs until LE goes low,
which sounds like the clock on the 374. This looks like either a low or
high could be latched on the ouput while LE is high.

What im looking for is a latch which will only trip on and not latch off
also. A thyristor is idea, its a oneshot deal, once its on, its on. I want
my inputs on my "373" to latch on and stay on, then I want to keep those
latched outputs on, and disable the 373 form any further inputs. Though I
must point out that in the time it takes for the enable pin to go high, the
data may have changed on the inputs in which case I could loose my latch ON
and latch off.

I could draw the current circuit I have out, though its a bit more involved,
since the outputs of my buffer chip are actually feed back into the inputs.
I know this sounds daft, but im working with a bi-directional data bus which
has a special setup. And once the 1 input has been latched on, and then ORed
tot he enable, they are also ANDed together, so each of the 4 origonal input
are then set high, though this can casue the latch to latch the other 3
inputs on, so theres actually 4 zeners dropping the voltages on each of the
data lines, this is to give the enable pin a 5volt "head start" on the input
lines. I found that pulsing the enable high at the same time as the data
lines does not work, which is why I have to make sure the chip is disabled
before the "loop back" voltages trigger the other 3 latches.

I hope this makes sence, its a simple circuit, though theres a lot of parts
involved and im just trying to combine the latch and 3state buffers into 1
latch IC.......

Chris

 

[John Fields]

On Thu, 20 May 2004 20:38:36 +0100, "exxos" <exxos@home.co.uk> wrote:

What I have at the moment which works fine, is a 3state buffer, 74HC541, and
4 2N5060 thyristors, when the 541 has a input it goes right though the
buffer.... the buffer then triggers the thyristor which latches on and stays
on. The voltages on the thyristor are also feed back into the 3state buffer
turning it off. Now should a input to the buffer rise again, nothing will
happen, and no latching will happen since the thyristors are isolated from
the input lines via the 541 buffer. This all works fine.......

Now what I want to do is do the same thing but with 1 IC, A latch IC. Now I
want the same to happen but without using seperate devices. I want to latch
a input line (like my thyristors does), then once one of the 4 latches are
on, I then want to isoltate the latches from the incomming inputs (like me
3state buffer does).

In anycase, the outputs of the buffer are going via a 4input OR gate and
then going to the 3state pin on the buffer. So when any input goes high,
that input is latched on and the buffer is disabled from any further inputs.

What I am not sure of is the 373 latch. If I have a input, normally to latch
it you have to pulse the clock pin to clock it into the latch. Normally
AFAIK if the clock pin stays high whatever is on the inputs appears on the
ouputs , and latched when the clock line goes low. (this is what the 374
looks to do).

I am not sure how the data and enable are working on the 373. I assume while
LE is high any data will be latched. Though the datasheet seems unclear if
its actually latched, or the outputs are just following the inputs (as it
would while the clock on the 374 were high).

---
It's a _transparent_ latch, so whatever's on the input will go
straight through to the corresponding output as long as LE is high.
Then, when LE goes low, whatever state the input was in when LE went
low is the state the output will remain in, no matter what the input
does, as lond as LE remains low. Actually, there are two times you
have to watch out for to make sure the latch latches properly when LE
goes low; setup time and hold time. Setup time is how long data has
to be stable on the input _before_ LE goes low for the output to
capture the data properly, and hold time is how long the input data
has to remain stable _after_ LE goes low. For Philips HC running at
5V, Tsu is 15ns minimum, and Th is 5ns.
---

I assume that on the 373 while LE is high, the data is latched, which looks
to me asif the outputs are just following the inputs until LE goes low,
which sounds like the clock on the 374. This looks like either a low or
high could be latched on the ouput while LE is high.

---
_Nothing_ is latched on the 373 when LE is high, its inputs just pass
through to the outputs. A 373 is a transparent latch, and a 374 is a
"D" type flip-flop, two _completely_ different animals. Unlike a
transparent latch, the "D" type flip-flop's outputs will _never_
follow its inputs, but rather , the flip-flop will capture whatever
state the input was in when the clock input goes high and transfer
that state to the output. If the inputs move around after the clock
goes high, nothing will happen on the outputs, and nothing will happen
when the clock goes low, and nothing will happen while the clock is
low, _no matter what_ the input does. The only time anything will
happen is during the time the clock goes high, subject to the setup
and hold time limitations for the chip.
---

What im looking for is a latch which will only trip on and not latch off
also. A thyristor is idea, its a oneshot deal, once its on, its on. I want
my inputs on my "373" to latch on and stay on, then I want to keep those
latched outputs on, and disable the 373 form any further inputs. Though I
must point out that in the time it takes for the enable pin to go high, the
data may have changed on the inputs in which case I could loose my latch ON
and latch off.

---
What??? If that's true, then this thing is going to wind up chasing
its own tail and you may have bigger problems than you think you do...


What kinds of times are you talking about, anyway?

That is, if one of the inputs goes high what's the minimum time that
can occur before another one goes high? Also, if one input goes high,
what's the minimum time that can occur before it goes low again?

A timing diagram would be nice...
---

I could draw the current circuit I have out, though its a bit more involved,
since the outputs of my buffer chip are actually feed back into the inputs.
I know this sounds daft, but im working with a bi-directional data bus which
has a special setup. And once the 1 input has been latched on, and then ORed
tot he enable, they are also ANDed together, so each of the 4 origonal input
are then set high, though this can casue the latch to latch the other 3
inputs on, so theres actually 4 zeners dropping the voltages on each of the
data lines, this is to give the enable pin a 5volt "head start" on the input
lines. I found that pulsing the enable high at the same time as the data
lines does not work, which is why I have to make sure the chip is disabled
before the "loop back" voltages trigger the other 3 latches.

I hope this makes sence, its a simple circuit, though theres a lot of parts
involved and im just trying to combine the latch and 3state buffers into 1
latch IC.......

---
If you can answer the timing questions I asked and post a timing
diagram, there's a good (maybe...) chance we can clean the circuit up
and get rid of all that crap.

--
John Fields

 

[exxos]

It's a _transparent_ latch, so whatever's on the input will go
straight through to the corresponding output as long as LE is high.
Then, when LE goes low, whatever state the input was in when LE went
low is the state the output will remain in, no matter what the input
does, as lond as LE remains low. Actually, there are two times you
have to watch out for to make sure the latch latches properly when LE
goes low; setup time and hold time. Setup time is how long data has
to be stable on the input _before_ LE goes low for the output to
capture the data properly, and hold time is how long the input data
has to remain stable _after_ LE goes low. For Philips HC running at
5V, Tsu is 15ns minimum, and Th is 5ns.

I looked into this today, I dont think either of those latches will work
since I'm not using anything like a clock......

---

I assume that on the 373 while LE is high, the data is latched, which
looks
to me asif the outputs are just following the inputs until LE goes low,
which sounds like the clock on the 374. This looks like either a low or
high could be latched on the ouput while LE is high.

---
_Nothing_ is latched on the 373 when LE is high, its inputs just pass
through to the outputs. A 373 is a transparent latch, and a 374 is a
"D" type flip-flop, two _completely_ different animals. Unlike a
transparent latch, the "D" type flip-flop's outputs will _never_
follow its inputs, but rather , the flip-flop will capture whatever
state the input was in when the clock input goes high and transfer
that state to the output. If the inputs move around after the clock
goes high, nothing will happen on the outputs, and nothing will happen
when the clock goes low, and nothing will happen while the clock is
low, _no matter what_ the input does. The only time anything will
happen is during the time the clock goes high, subject to the setup
and hold time limitations for the chip.
---

which is what I thought...

What im looking for is a latch which will only trip on and not latch off
also. A thyristor is idea, its a oneshot deal, once its on, its on. I
want
my inputs on my "373" to latch on and stay on, then I want to keep those
latched outputs on, and disable the 373 form any further inputs. Though I
must point out that in the time it takes for the enable pin to go high,
the
data may have changed on the inputs in which case I could loose my latch
ON
and latch off.

---
What??? If that's true, then this thing is going to wind up chasing
its own tail and you may have bigger problems than you think you do...

I dont have a problem with the circuit im using, im just trying to see if It
can be made more simple.

What kinds of times are you talking about, anyway?

That is, if one of the inputs goes high what's the minimum time that
can occur before another one goes high? Also, if one input goes high,
what's the minimum time that can occur before it goes low again?

A timing diagram would be nice...
---

Its all a oneshot deal, any of the 4 inputs can go high at any time, its not
THAT important, normally only 1 goes high, though on some cases 2 can go
high at the same time, its not a problem. Which ever lines went high are
latched on. then the biffer is disabled so if any other lines go high they
are ignored.

If you can answer the timing questions I asked and post a timing
diagram, there's a good (maybe...) chance we can clean the circuit up
and get rid of all that crap.

The only timing line to be aware of is that the enable pin on my buffer must
go high Before the inputs are all pulled high. You will probably understand
if you take a look at the diagram I did just at
http://exxos.250free.com/temp/cct.zip

The slight "floors" are the enable pin on the 5vdc buffer chip is being
pulsed to 12v. Though ive not worked that problem out yet. The inputs on D0
come in normally at 12VDC, there is a zener there to drop the voltage to the
buffer. The buffer triggers a thyristor, which turns on a LED and also a PNP
transistor. This in turn pulls up D0 upto 12 volts. The input zener now
makes this line lagg behind the enable line by about 5 volts. this ensures
the chip is disabled before the voltage rises on the D0 input and retriggers
the latch..... this isn't a problem BUT.......

at the point "A" are wired in parallel to 4 exact same circuits. They will
simple be D0,D1,D2,D3. Now when any of the PNP transistors pull up the "A"
line, this voltage is feed back into D0,D1,D2,D3. The Latch MUST be disabled
else this pulse would cause the remains thyristors to latch on.

The cap and resistor is there since the buffer seems to pulse its outputs on
powerup so its disabled on powerup.

The OUT0 line is to trigger another circuit, though this is wired to point
"A" so not important in this case.

The buffer should really be a CMOS type, though I am not sure with testing
if a CMOS will have enough to turn on the thyristor, I imagine it would,
though its only a test circuit and I am trying to find a way to simplify it.

I hope this makes sence, as I said the circuit works fine though its a bit
long winded I think. I think if there was a TTL latch where I can
disconnect the inputs like my buffer does, then I wouldn't need the buffer
or the thyristor. There would probably be enough current to pull up the "A"
line also so the PNP transistor wouldn't be needed.

Chris

--
John Fields

 

[Bob Myers]

"exxos" <exxos@home.co.uk> wrote in message
news:40ae36cc$0$20511$cc9e4d1f@news-text.dial.pipex.com...

It's a _transparent_ latch,

"Oh, aye, and d'ye think that might be WORTH somethin' to ya,
laddie?"

OK, sorry...had a brief Star Trek IV flash there...I'm better now....



Bob M.

 

[exxos]

"Bob Myers" <nospamplease@address.invalid> wrote in message
news:gwsrc.2071$eE4.771@news.cpqcorp.net...

"exxos" <exxos@home.co.uk> wrote in message
news:40ae36cc$0$20511$cc9e4d1f@news-text.dial.pipex.com...


It's a _transparent_ latch,

"Oh, aye, and d'ye think that might be WORTH somethin' to ya,
laddie?"

OK, sorry...had a brief Star Trek IV flash there...I'm better now....



Bob M.

lol, well..... I'm sure I can redesign the thing, after all I designed it
in the first place, I maybe slow but I get there in the end I'd rather
get there sooner tho though you can't change the laws of physics! (can
have a bloody good go tho

Chris

 

[John Fields]

On Fri, 21 May 2004 18:07:29 +0100, "exxos" <exxos@home.co.uk> wrote:

Its all a oneshot deal, any of the 4 inputs can go high at any time, its not
THAT important, normally only 1 goes high, though on some cases 2 can go
high at the same time, its not a problem. Which ever lines went high are
latched on. then the biffer is disabled so if any other lines go high they
are ignored.

Click on this ---> b5psa0t89n946e14narqgq9fm6m9srkrc3@4ax.com

On your drawing:

1. for a 12v signal input, the Zener and the 100k resistor should be
swapped, with the anode of the Zener going to ground.

2. The PNP is in backwards; the emitter should be going to 12V and the
collector should be going to ground.

--
John Fields

 

[exxos]

"John Fields" <jfields@austininstruments.com> wrote in message
news:6jhsa016gins0sc9khtg3f4sm3ce84cgkf@4ax.com...

On Fri, 21 May 2004 18:07:29 +0100, "exxos" <exxos@home.co.uk> wrote:


Its all a oneshot deal, any of the 4 inputs can go high at any time, its
not
THAT important, normally only 1 goes high, though on some cases 2 can go
high at the same time, its not a problem. Which ever lines went high are
latched on. then the biffer is disabled so if any other lines go high
they
are ignored.

Click on this ---> b5psa0t89n946e14narqgq9fm6m9srkrc3@4ax.com

On your drawing:

1. for a 12v signal input, the Zener and the 100k resistor should be
swapped, with the anode of the Zener going to ground.

true, but the zener does 2 things, it also drop the "A" voltage by 5 volts,
this ensures enable hits 5volts before the input does, when enable is at
12volts, the input is then at 5 volts, but then its too late for the input
to do anything since the buffer is disabled.

2. The PNP is in backwards; the emitter should be going to 12V and the
collector should be going to ground.

ah, might be on the drawing, I used a NPN to start with but then changed to
a PNP, on the circuit it works correctly so assume its a draw error......

Chris

--
John Fields

 

[John Fields]

On Fri, 21 May 2004 21:57:21 +0100, "exxos" <exxos@home.co.uk> wrote:

"John Fields" <jfields@austininstruments.com> wrote in message
news:6jhsa016gins0sc9khtg3f4sm3ce84cgkf@4ax.com...
On Fri, 21 May 2004 18:07:29 +0100, "exxos" <exxos@home.co.uk> wrote:


Its all a oneshot deal, any of the 4 inputs can go high at any time, its
not
THAT important, normally only 1 goes high, though on some cases 2 can go
high at the same time, its not a problem. Which ever lines went high are
latched on. then the biffer is disabled so if any other lines go high
they
are ignored.

Click on this ---> b5psa0t89n946e14narqgq9fm6m9srkrc3@4ax.com

On your drawing:

1. for a 12v signal input, the Zener and the 100k resistor should be
swapped, with the anode of the Zener going to ground.


true, but the zener does 2 things, it also drop the "A" voltage by 5 volts,
this ensures enable hits 5volts before the input does, when enable is at
12volts, the input is then at 5 volts, but then its too late for the input
to do anything since the buffer is disabled.




2. The PNP is in backwards; the emitter should be going to 12V and the
collector should be going to ground.


ah, might be on the drawing, I used a NPN to start with but then changed to
a PNP, on the circuit it works correctly so assume its a draw error......

---
Did you get the schematic I posted for you?

Since I took a couple of hours out of my life to come up with a
solution for you, for free, I'd like to know.

--
John Fields

 

[exxos]

---
Did you get the schematic I posted for you?

Since I took a couple of hours out of my life to come up with a
solution for you, for free, I'd like to know.

I clicked on the URL though it appears to be a Email address since it has
the @ in it, in anycase I can't download anything from it no matter what I
do?

Chris

--
John Fields

 

[John Fields]

On Sat, 22 May 2004 23:54:20 +0100, "exxos" <exxos@home.co.uk> wrote:

---
Did you get the schematic I posted for you?

Since I took a couple of hours out of my life to come up with a
solution for you, for free, I'd like to know.

I clicked on the URL though it appears to be a Email address since it has
the @ in it, in anycase I can't download anything from it no matter what I
do?

---
It's a link to the schematic I posted on
alt.binaries.schematics.electronic.

If your ISP doesn't carry abse let me know and I'll email it to the
email address you've posted here, otherwise email me with your real
email address and I'll email it to you there.

--
John Fields

 

[Mjolinor]

---
It's a link to the schematic I posted on
alt.binaries.schematics.electronic.

If your ISP doesn't carry abse let me know and I'll email it to the
email address you've posted here, otherwise email me with your real
email address and I'll email it to you there.

--
John Fields

Please explain this, I got a "new email" box up, (Microcrap SW)

Yes I will take the stick that will obviously come from admitting that I use
Outlook Express and explanations that say "change your news reader" are not
really what I am looking for

 

[exxos]

"John Fields" <jfields@austininstruments.com> wrote in message
news:tmmva0pr1ctj5kviu0heqqh6vro63gkk4f@4ax.com...

On Sat, 22 May 2004 23:54:20 +0100, "exxos" <exxos@home.co.uk> wrote:


---
Did you get the schematic I posted for you?

Since I took a couple of hours out of my life to come up with a
solution for you, for free, I'd like to know.

I clicked on the URL though it appears to be a Email address since it has
the @ in it, in anycase I can't download anything from it no matter what
I
do?

---
It's a link to the schematic I posted on
alt.binaries.schematics.electronic.

If your ISP doesn't carry abse let me know and I'll email it to the
email address you've posted here, otherwise email me with your real
email address and I'll email it to you there.

ah, will have to add a new news server since im only using the text server,
will have a look when its eventually downloads the list......... the mail
addy I use here isn't valid btw.....

Chris

--
John Fields

 

[exxos]

"John Fields" <jfields@austininstruments.com> wrote in message
news:tmmva0pr1ctj5kviu0heqqh6vro63gkk4f@4ax.com...

On Sat, 22 May 2004 23:54:20 +0100, "exxos" <exxos@home.co.uk> wrote:


---
Did you get the schematic I posted for you?

Since I took a couple of hours out of my life to come up with a
solution for you, for free, I'd like to know.

I clicked on the URL though it appears to be a Email address since it has
the @ in it, in anycase I can't download anything from it no matter what
I
do?

---
It's a link to the schematic I posted on
alt.binaries.schematics.electronic.

If your ISP doesn't carry abse let me know and I'll email it to the
email address you've posted here, otherwise email me with your real
email address and I'll email it to you there.

--
John Fields

interesting design, I will study this in the morning, what IC are you using
there ? its a little unclear in the pdf. Anyway, thanks for taking the time
to look into this, I will study it in a few hours when ive woke up, if I
have the right gates I will see what I can do about building it on
breadboard and see how it works in realtime.

thanks,
Chris