LFSR 32-bit parity generator

[Daku]

Could some Verilog guru please provide some pointers ? I am trying to
create a LFSR 32 bit
parity generator. I am not sure where exactly
to put the XORs, and the total number of these.
Any example code, etc., or pointers to such
would be of immense help. Thanks in advance.

 

[Muzaffer Kal]

On Sat, 12 Mar 2011 08:21:28 -0800 (PST), Daku <dakupoto@gmail.com>
wrote:

Could some Verilog guru please provide some pointers ? I am trying to
create a LFSR 32 bit
parity generator. I am not sure where exactly
to put the XORs, and the total number of these.
Any example code, etc., or pointers to such
would be of immense help. Thanks in advance.

here it is:
http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[gabor]

On Saturday, March 12, 2011 2:35:44 PM UTC-5, Muzaffer Kal wrote:

On Sat, 12 Mar 2011 08:21:28 -0800 (PST), Daku <daku...@gmail.com
wrote:

Could some Verilog guru please provide some pointers ? I am trying to
create a LFSR 32 bit
parity generator. I am not sure where exactly
to put the XORs, and the total number of these.
Any example code, etc., or pointers to such
would be of immense help. Thanks in advance.

here it is:
http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

That's a great reference. You should note
that the standard for naming the register
bits is [N:1] rather than the more typical
[N-1:0] when you reference the bit numbers
in the table. So for example the 32-bit
maximal LFSR described as 1,2,22,32 includes
the LSB and MSB of the shift register in the
XOR inputs.

-- Gabor