J
Joe Chisolm
Guest
On Fri, 20 Sep 2013 12:08:23 -0500, Tim Wescott wrote:
I agree with Tim on using an emulator if you can. I do not see why
you need to get down to the gate level. I have never done
any work with this CPU but a quick search brings up many emulators
for the TI-99 game system that, from what I read, used the TMS9900.
Pull the core cpu emulator code out of one of these and put it in
a fast micro, possibly one that will run out of SRAM. You can tie
the micro's ISR into the emulator so you get good interrupt timing.
You will still probably have to hang some interface logic around
the micro.
The nice thing about using the emulator is you can get it running on
a PC or even a target micro development board, and get the basic
bugs worked out.
The HDL approach would be a very interesting project and a lot of
fun but I think you are under estimating the level of effort to
take something from OpenCores and get it to production level.
--
Chisolm
Republic of Texas
On Fri, 20 Sep 2013 06:59:18 -0700, ditiris wrote:
Wow, lots of activity since I last checked. To answer some questions:
This is for business, not an educational exercise.
The chip is in the TI 9900 family (weird architecture).
I will need to reproduce all logical levels into and out of the chip
with timing faithful to the original chip (or as close as I can get it,
divide is going to be an issue). A lot of the circuits on the board are
old 54-series discrete logic, so those all get sucked in too, so we
wind up emulating the tri-state internal to the FPGA. Outside, we have
lots of level converters and discrete control to faithfully replicate
the 5V tri-state.
The application is real-time, so I think that rules out software
emulation. I explored that path a bit, but after reading up on SNES
emulators (1991 3.58MHz 16-bit CPU) and finding that most are heavily
optimized and largely written in assembly, I figured HDL was a better
cost-value-risk proposal. When I got to the part how most software
emulators only work most of the time and they actually need a 3GHz
multi-core CPU to accurately model the SNES hardware delays in all
cases, I was really convinced HDL was the way to go...
Software emulators are apparently fine legally, and I think that's a
close corollary to what we'll be doing. Given that Tekmos has a
business at all, we should really be fine.
However, we're still going to consult with a lawyer just to be sure.
Legal problems aside, if there's an emulator out there that's 100%
accurate but for timing, and if you can do it this way, I'd run it fast
enough so that the slowest instruction happens on time, then slow all
the other ones down to match.
That gets difficult if some execution times are data-dependent.
As far as actual legal problems -- I think you're OK, but talking to a
lawyer is a Good Idea.
First TI would have to care. Then they'd have to dare. Your biggest
problem would be some TI lawyer trying to justify his pay by finding an
encroachment, and you getting squished long before you can win just
because they're so much bigger than you.
I agree with Tim on using an emulator if you can. I do not see why
you need to get down to the gate level. I have never done
any work with this CPU but a quick search brings up many emulators
for the TI-99 game system that, from what I read, used the TMS9900.
Pull the core cpu emulator code out of one of these and put it in
a fast micro, possibly one that will run out of SRAM. You can tie
the micro's ISR into the emulator so you get good interrupt timing.
You will still probably have to hang some interface logic around
the micro.
The nice thing about using the emulator is you can get it running on
a PC or even a target micro development board, and get the basic
bugs worked out.
The HDL approach would be a very interesting project and a lot of
fun but I think you are under estimating the level of effort to
take something from OpenCores and get it to production level.
--
Chisolm
Republic of Texas