Lattice Announces EOL for XP and EC/P Product Lines

[rickman]

On 7/30/2013 10:25 PM, Gabor wrote:

On 7/30/2013 9:03 PM, Rob Doyle wrote:
On 7/30/2013 11:37 AM, rickman wrote:
Spartan 6 parts give a *lot* more functionality, but I'd have to use
a 256 pin 1.0 mm BGA *and* external flash *and* the 1.2 volt supply
*and* they are twice the price. Maybe I'll talk to the disties.
Maybe they can do something about the price at least.

The smaller Spartan 6 parts do come in a 144 pin TQFP package. Too small?

Rob.

Apparently the 144 TQ package is too big (physically). And once you
look at a 256-ball 1mm BGA you could find any number of devices
including those from Lattice (XP2?). For internals, the smallest
Spartan 6 is about the size of the original XP part he was using.

As to price, we never pay anything near list for Xilinx parts, but
we don't get the same steep discount on Spartan 6 as we do on other
series.

There is some irony, the parts the smallest Spartan 6 comes in are *too*
small in terms of ball pitch. They require PCB design rules down to 3/3
trace/space. To get a FTG256 BGA you have to bump up to the next size
which is some four times bigger than the part I'm using now. It has
nearly 6K LUTs and they are 6 input LUTs rather than 4 input. It also
has tons of multipliers and RAM, so it is a *lot* more device. The
Digikey price is about double too..., but that can be negotiable.

--

Rick

 

[rickman]

On 7/30/2013 2:37 PM, rickman wrote:

I have yet to check out the Altera line. I don't remember them having
anything I liked in a nice package. But that will be something to do
later today. I guess I should check out the Micro-Semi line as well.
It's been a while since I looked hard at their parts and, oh yeah, there
is the PSOC from Cypress. I don't think that was an option at the time I
did this design.

I went to the Cypress web site and I can't find a data sheet on their
PSOC parts. They also encrypt the info on the broad classes of devices
behind marketing speak. So I can't even get a feel for what they are
capable of.

--

Rick

 

[GaborSzakacs]

rickman wrote:

On 7/30/2013 9:50 PM, Jon Elson wrote:
rickman wrote:


The smallest Spartan 3A is under $10, the 3AN is about $15.

Actually my main concern with the external flash is the whole JTAG
programming at the factory and/or lab thing, but there are likely many
ways to deal with that including having them programmed before assembly.
It is just that I've been using these Flash FPGAs for some time now
and I'm very used to them.

The 3AN can be programmed by JTAG, the SST serial EPROM I use on
the 3A is not JTAG, although a flexible programmer or tester
could easily be "taught" the protocol. I chose this device
so I could have field-replaceable firmware. I had to make an
SO-8 to DIP converter board though, as the SST chip is only
available in a couple SMT packages.

Yeah, I am supposed to provide JTAG programmability through the
equipment this daughtercard is plugged into. That is, I provide the
JTAG port, it is up to them to do the software to program it. That is
one of my concerns with an external seral prom. May not be easy to do
in an 8 pin package... But if they can learn the protocol, maybe that
would work too. We'll see. After 5 years we still have not required
this functionality. But I'll be pushing for increased capability in the
new version to allow it to be sold into new areas. So remote updates
may be more important then.

Most recent parts from Xilinx including Spartan 3A have SPI master
mode configuration, requiring nothing extra over the SPI flash itself
and a handful of resistors. Indirect SPI flash programming over
JTAG is supported by Impact, and you can generate SVF files to
do the programming with an embedded processor. Also because the
pins used for SPI config become I/O after config, you can use
the SPI flash in your design, and possibly come up with a more
"native" solution to field updates (without using JTAG).

--
Gabor

 

[rickman]

On 7/31/2013 5:13 PM, GaborSzakacs wrote:

Most recent parts from Xilinx including Spartan 3A have SPI master
mode configuration, requiring nothing extra over the SPI flash itself
and a handful of resistors. Indirect SPI flash programming over
JTAG is supported by Impact, and you can generate SVF files to
do the programming with an embedded processor. Also because the
pins used for SPI config become I/O after config, you can use
the SPI flash in your design, and possibly come up with a more
"native" solution to field updates (without using JTAG).

I'm not sure what the use of Impact implies. Does that mean connecting
a PC with a dongle cable? That would be used in the factory perhaps,
but in the field they want to use an CPU to drive the JTAG signals.
They have that working for an Altera part, but not yet for the Lattice
part and of course not for any Xilinx parts.

--

Rick

 

[Jon Elson]

rickman wrote:

I'm not sure what the use of Impact implies. Does that mean connecting
a PC with a dongle cable? That would be used in the factory perhaps,
but in the field they want to use an CPU to drive the JTAG signals.
They have that working for an Altera part, but not yet for the Lattice
part and of course not for any Xilinx parts.

Yes, you certainly can do that, and Xilinx has some articles

on how to write your computer code to take a .bit file loaded into
a processor's EPROM and perform the various modes of download
available. There is serial config, parallel config, JTAG config,
etc. To do this from a CPU, you want slave mode, where the
CPU clocks the bits into the FPGA. For a serial EPROM chip you
select master serial, so the FPGA generates the bit clock.
The newer FPGAs have almost too MANY modes of configuration.

Jon

 

[Chris]

Rick... I check the Actel/Microsemi lead you started down on the original post, they have options available in your target size, 100 pin QFP, are flash based/reprogrammable over JTAG and I think should have very similar power requirements to your original design. I am looking at this chip, available today on digikey: AGL250V2-VQG100, 14 mm2, $25.40, 68 I/O and a fair amount of logic. If you don't need that much logic and want a cheaper part they go down from there in the same package.

 

[Svenn Are Bjerkem]

kl. 00:54:41 UTC+2 wednesday 31. july 2013 rickman wrote:

In fact, I'm skipping Altera for the moment and skipping over to
MicroSemi and Cypress to see if their combination CPU/Logic devices
might do the job well and let me eliminate the stereo CODEC to (another
part that could go obsolete at any time). I seem to recall that the
Cypress part might be just the ticket but the MicroSemi part runs some
$50 at the low point. The current Lattice part is running under $10.

We've got a quote for the Microsemi SF2 M2S010 (without T) somewhere in the middle of that price difference in low volume. The features of SF2 somehow justified the additional price because we could avoid a separate flash and MCU externally. The flexibility in configuration of the FPGA and MSS and hard preipherals also give us design freedom. Low power consumption was definitively something worth a bit extra.

--
Svenn

 

[rickman]

On 8/1/2013 3:21 AM, Svenn Are Bjerkem wrote:

kl. 00:54:41 UTC+2 wednesday 31. july 2013 rickman wrote:
In fact, I'm skipping Altera for the moment and skipping over to
MicroSemi and Cypress to see if their combination CPU/Logic devices
might do the job well and let me eliminate the stereo CODEC to (another
part that could go obsolete at any time). I seem to recall that the
Cypress part might be just the ticket but the MicroSemi part runs some
$50 at the low point. The current Lattice part is running under $10.

We've got a quote for the Microsemi SF2 M2S010 (without T) somewhere in the middle of that price difference in low volume. The features of SF2 somehow justified the additional price because we could avoid a separate flash and MCU externally. The flexibility in configuration of the FPGA and MSS and hard preipherals also give us design freedom. Low power consumption was definitively something worth a bit extra.

Yes, each project has its own requirements so some will justify a higher
price for the improved integration. I am not so familiar with the
Microsemi part and I not had time to dig into their offerings. I don't
even know if they have anything new in the last year or two.

The main stumbling block for the Cypress part is the lack of CD quality
CODEC I believe. But that is only a $3 part at most. There are also
some op amps on the board which I doubt can be replaced since at least
four of them are used to drive a 12 volt supply into a 50 ohm load (8
Vp-p IIRC). The remaining parts are analog switches on the analog I/O,
analog switches on the digital I/O to act as 5-3 volt level converters
and a two channel RS-422 input/output chip. I doubt any of this can be
pulled into the Microsemi part leaving us with this possibly replacing
the existing FPGA and the CODEC at best. So it would be hard to justify
replacing what is otherwise $15 worth of parts with a $30 part if I read
your post correctly. By low volume I assume you mean qty 100 ball park.

Funny about Cypress. I seem to recall their web site having gone
downhill over the last few years. When I tried to download a data sheet
on their parts I couldn't find one! They have links for their software
and for samples, but none for a data sheet!!!? Maybe it is embedded in
their development software? They also give a crappy overview of their
parts. So far I haven't figured it out but I guess it is worth a second
try.

--

Rick

 

[rickman]

On 7/31/2013 6:23 PM, Jon Elson wrote:

rickman wrote:


I'm not sure what the use of Impact implies. Does that mean connecting
a PC with a dongle cable? That would be used in the factory perhaps,
but in the field they want to use an CPU to drive the JTAG signals.
They have that working for an Altera part, but not yet for the Lattice
part and of course not for any Xilinx parts.

Yes, you certainly can do that, and Xilinx has some articles
on how to write your computer code to take a .bit file loaded into
a processor's EPROM and perform the various modes of download
available. There is serial config, parallel config, JTAG config,
etc. To do this from a CPU, you want slave mode, where the
CPU clocks the bits into the FPGA. For a serial EPROM chip you
select master serial, so the FPGA generates the bit clock.
The newer FPGAs have almost too MANY modes of configuration.

I think what you are describing is rather different. This is the slave
serial config mode which is somewhat limited in functionality. The
interface my customer has provided is intended to use a JTAG interface.
In the case of the serial EEPROM the CPU would either program the
EEPROM directly or drive the JTAG on the FPGA to program the EEPROM.

I'm pretty sure the customer does *not* want to load the part every time
it is booted, just once in a programming mode, then the board loads
itself when it boots up. I'm not sure if this is what you were
describing or not.

--

Rick

 

[Anssi Saari]

GaborSzakacs <gabor@alacron.com> writes:

I'm pretty sure that the 144-pin package is the smallest with flash.

The data sheet lists Spartan3 200AN and 50AN parts with VQ100 package
and 68 user I/Os. Might be those packages are EOL though.

 

[rickman]

On 8/1/2013 3:21 AM, Svenn Are Bjerkem wrote:

kl. 00:54:41 UTC+2 wednesday 31. july 2013 rickman wrote:
In fact, I'm skipping Altera for the moment and skipping over to
MicroSemi and Cypress to see if their combination CPU/Logic devices
might do the job well and let me eliminate the stereo CODEC to (another
part that could go obsolete at any time). I seem to recall that the
Cypress part might be just the ticket but the MicroSemi part runs some
$50 at the low point. The current Lattice part is running under $10.

We've got a quote for the Microsemi SF2 M2S010 (without T) somewhere in the middle of that price difference in low volume. The features of SF2 somehow justified the additional price because we could avoid a separate flash and MCU externally. The flexibility in configuration of the FPGA and MSS and hard preipherals also give us design freedom. Low power consumption was definitively something worth a bit extra.

I had a chance to look at the Smart Fusion 2 devices, and they seem to
be too much device for this project. The M2S005 would likely be a good
fit with a lot more logic than needed, but the smallest package it comes
in is a fine pitch BGA with 400 pins! I guess they are targeting much
larger apps than mine.

I still need to take a better look at the Cypress parts if I can figure
out how to get a data sheet.

--

Rick

 

[Chris]

Rick,

It seems to me that you have changed your goals around a bit and it is not clear to me exactly what you are looking for anymore but from what I can gather I still think you are missing out on a decent choice if you are ignoring the actel/microsemi igloo parts. Take another look at the agl250 line. If you need the smaller quad flat pack it is there, I would imagine there is plenty of logic for your existing product and it is inexpensive. They have a chip in the same package with a cortex m1 if you want an embedded uC too.

I personally prefer to design with Xilinx first then altera then actel but will definitely go with actel when the design needs it, they just tend to run a bit slower than what I like. I have looked at using the cypress chips before for the USB capability back around 2005 but was not able to get the windows side working right with the jungo driver so went with the USB to uart parts from ftdi instead. Never looked back to cypress or jungo since then.

 

[rickman]

On 8/4/2013 4:09 PM, Chris wrote:

Rick,

It seems to me that you have changed your goals around a bit and it is not clear to me exactly what you are looking for anymore but from what I can gather I still think you are missing out on a decent choice if you are ignoring the actel/microsemi igloo parts. Take another look at the agl250 line. If you need the smaller quad flat pack it is there, I would imagine there is plenty of logic for your existing product and it is inexpensive. They have a chip in the same package with a cortex m1 if you want an embedded uC too.

The goal is to live a rich, full life... There are any number of
ways to do that.

I have gone through all the major FPGA makers, including MicroSemi and
created a spread sheet of the devices which might substitute for the
Lattice part that has been discontinued. I may have given the Igloo
parts short shrift because I seem to recall they use Versa tiles for
both logic an FFs, so you need twice as many if you need both FFs and 4
input LUTs. The Lattice FPGA being replaced has some 3000 LUTs and 3000
FFs, IIRC so the AGLN250 might suit the requirement. It would be nicer
if the new device offered some new capability such as more logic and/or
multipliers. So I should at least include this part in my selection
even if it does not provide any new capabilities.

I personally prefer to design with Xilinx first then altera then actel but will definitely go with actel when the design needs it, they just tend to run a bit slower than what I like. I have looked at using the cypress chips before for the USB capability back around 2005 but was not able to get the windows side working right with the jungo driver so went with the USB to uart parts from ftdi instead. Never looked back to cypress or jungo since then.

As to my seeming switching of requirements, we *have* to replace the
FPGA. There is also a CODEC from AKM on the board which could be hard
to replace should it also go obsolete. It is just as old as the FPGA
and I have no insight about when AKM might obsolete it. Everything else
on the board is second sourced. So if we are building a new model, I
want to have a plan for providing some assurance the CODEC won't cause
another redesign in a couple of years.

One way of doing this is to combine the CODEC function with the FPGA
(hence looking at the Microsemi MCU/FPGA device which turns out to be
rather pricey) or possibly use an MCU (with adequate analog I/O) and a
smaller FPGA. Only a portion of the current FPGA design has to be in an
FPGA, most of it is slow logic can be turned into software.

SiLabs seems to make an 8051 type chip with 16 bit ADCs and fast 12 bit
DACs. I might be able to dither the DACs to provide higher resolution
on the output. I need to also look at Cirrus Logic. I seem to recall
they make some parts that might work. Its hard because of the limited
board space, but two smaller devices might actually take up less board
space than one large one. Providing a 5 volt tolerant interface would
also eliminate some other chips and free up more board space.

Both ADI and TI have DSP/CODEC devices, but they aren't designed for
general purpose programming and just don't suit the need.

--

Rick

 

[rickman]

On 8/5/2013 12:42 AM, Chris wrote:

Well I am jealous that sounds like a fun project. One other thing that came to mind as this was going through my head today was the fpslic from atmel, we looked at using one a while back but ultimately decided on splitting the design into a cpld (coolrunner) and an atmega128.

Best of luck and let me know what you decide on, it is interesting to me.

Wow! I had no idea they still made the FPSLIC. That is *very* long in
the tooth and I believe it never had much market penetration so that I
expect many potential users were put off thinking it would be scrapped.
Actually, if we had any assurance that would be made for the next 5-10
years, it likely could be a perfect fit. IIRC it had an AVR CPU and
some amount of the LUT based Atmel FPGA fabric. That would do a great
job of offloading the FPGA fabric with the AVR and likely is 5 volt
compatible so potentially saving some chips. But I'm pretty sure this
is not well supported and likely to be dumped any time. It's what, at
least 10 years old, maybe 15.

Heck, if the sky were the limit, I think this design could be done in
the GA144, a multiprocessor chip which I think is more like an FPGA with
processors in place of LUTs (I call it a FPPA, Field Programmable
Processor Array). But the company making them is very small and I doubt
they will be around in five years.

As to the "fun" aspect, yes, it is a bit of fun, but this is not a
salaried job, this is my *business*, so the seriousness takes away a lot
of the "fun". I need to impress the customer that I can give them a new
design that will last for at least 5 years and I would like to provide
them potential for new applications.

--

Rick

 

[rickman]

On 7/31/2013 7:48 PM, Chris wrote:

Rick... I check the Actel/Microsemi lead you started down on the original post, they have options available in your target size, 100 pin QFP, are flash based/reprogrammable over JTAG and I think should have very similar power requirements to your original design. I am looking at this chip, available today on digikey: AGL250V2-VQG100, 14 mm2, $25.40, 68 I/O and a fair amount of logic. If you don't need that much logic and want a cheaper part they go down from there in the same package.

Ok, I finally figured it out. Sometimes I am a little slow. The AGL
parts are just Igloo which is combined on a web page with the IGLOOe
parts. The link said IGLOO/e which made me think it was just the e
parts with the ARM M1 core enabled and I kept skipping that one.

Still, I find the parts to be a bit confusing. I'm not certain what the
difference between the IGLOO and the IGLOOnano is. It appears the nano
is slightly lower power, but I don't see just how much lower. The IGLOO
parts seem to come in an M1 version even without the 'e'. In fact the
lowest cost part in the AGL250 flavor (RoHS) is the M1 version! Not
sure just what that even means.

I think my main concern is that these parts are long in the tooth, but
I'll add them to my spread sheet since they are the only ones that can
fit the board without adding parts or going to a much tougher footprint
to use.

--

Rick

 

[Chris]

Well I am jealous that sounds like a fun project. One other thing that came to mind as this was going through my head today was the fpslic from atmel, we looked at using one a while back but ultimately decided on splitting the design into a cpld (coolrunner) and an atmega128.

Best of luck and let me know what you decide on, it is interesting to me.

 

[jg]

On Wednesday, July 31, 2013 6:37:21 AM UTC+12, rickman wrote:

It has 3000 LUTs which are around 80% used and the internal
configuration Flash saves space on the tiny, cramped board.

Mostly the alternatives are other Lattice devices, but none are a
perfect fit. XP2, XO2 and the iCE40 line. The ones that come in the
same package don't have as many LUTs, only 2100 which would require
using a soft CPU to implement the slow functions in fewer LUTs.

Someone mentioned Altera has a new family coming shortly, above the MAX V, which is looking backward next to Lattice.
So you could push them for more info on what packages/sizes they plan ?

-jg

 

[rickman]

On 8/11/2013 4:53 AM, jg wrote:

On Wednesday, July 31, 2013 6:37:21 AM UTC+12, rickman wrote:
It has 3000 LUTs which are around 80% used and the internal
configuration Flash saves space on the tiny, cramped board.

Mostly the alternatives are other Lattice devices, but none are a
perfect fit. XP2, XO2 and the iCE40 line. The ones that come in the
same package don't have as many LUTs, only 2100 which would require
using a soft CPU to implement the slow functions in fewer LUTs.

Someone mentioned Altera has a new family coming shortly, above the MAX V, which is looking backward next to Lattice.
So you could push them for more info on what packages/sizes they plan ?

Funny, I shot an email to my favorite distie and I was eventually
connected with an FAE. He is new to the company and indicated he would
be digging up an NDA to sign. I was a bit puzzled by this, it has been
a while since I was asked to sign an NDA to hear about new products. I
didn't hear back after a few days I called him. He was rather surprised
I was asking about the new line and asked how I even knew about it. I
told him I didn't know much other than it was a follow on to the Max V
and was pretty new. Seems it is so new that Altera hasn't spoken about
it other than under NDA, lol.

What I did get out of him was that currently they are pushing out a new
Stradix line IIRC and that would occupy them for most of 2014. If they
wouldn't have the Max V follow on in production until 2015 that is a bit
long for me to hold my breath. So I'm moving on... and I guess we
aren't doing the NDA... that's what I am required to say, lol

But at least Altera hasn't abandoned the Flash based logic area like
Xilinx. I like Lattice, but I'd hate for them to be the last man
standing in Flash FPGAs, well, other than MicroSemi assuming you count
them as being in the FPGA business. Just kidding...

--

Rick

 

Rick,

You might add MicroSemi Igloo2 to your list as well. A SmartFusion2 without the ARM, but still has the other hard-silicon interfaces.

Andy

 

[jg]

On Saturday, August 24, 2013 9:31:35 AM UTC+12, rickman wrote:

The favorable 100 pin QFP is not used in the
Igloo2 line and the Igloo line is rather long in the tooth.

I've noticed a significant trend from Asia, in Microcontrollers to offer
a choice of package-pitch, in particular, 64pin 0.8mm == same plastic as qfp100.

This allows higher yield PCB design rules.

It would be great if the FPGA/CPLD vendors grasped this.
-jg