Jihad needs scientists

Dan Bloomquist wrote:

MassiveProng wrote:


Note that TTL was the requisite defining element.
Click to expand...
Actually "the reason TTL was designed for 5 volts BCC"
was the requisite defining element. As usual, when
beaten to a logical pulp, one side attempted to shift
the goalposts.

That's another version of what amounts to the Godwin
alert, the discussion (as intended) is dead.

Next they'll argue I'm the one shifting the goalposts,
and I misunderstood. The record indicates otherwise.

No, it is, 'Jihad needs scientists'
Click to expand...
If we had to rely on some of the participants in this
thread for anything then the Jihadists would surely win.
 
Ken Smith wrote:

In article <et39ee$8ss_002@s948.apx1.sbo.ma.dialup.rcn.com>,
jmfbahciv@aol.com> wrote:

In article <et18sk$ki3$1@blue.rahul.net>,
kensmith@green.rahul.net (Ken Smith) wrote:

In article <et0nu2$8qk_001@s776.apx1.sbo.ma.dialup.rcn.com>,
jmfbahciv@aol.com> wrote:

In article <esuq2s$ds3$4@blue.rahul.net>,
kensmith@green.rahul.net (Ken Smith) wrote:

[....]

has run on 5V. The selection of 5V can be traced in part to the heater
voltage on tubes.

Now think about that over time.

Suddenly, you are arguing exactly my case and agreeing with me but putting
the above as a preface to it.

I wasn't agreeing to anything. By stripping the post to make it
appear that I was talking about a 5V factoid is blatant intellectual
dishonesty.


No, it was nothing of the sort. It was taking a section of what you said
without changing its meaning and pointing out that you had said "now think
about" in front of statements by you that agreed what what I had earlier
said.
Click to expand...
Holy Innocents, Batman!



You followed this with some other stuff that was so old hat it didn't need
a reply. We have beaten to death the topic of being compatible with the
installed base.
Click to expand...
 
Eeyore wrote:

"nonsense@unsettled.com" wrote:


Dan Bloomquist wrote:


MassiveProng wrote:


Note that TTL was the requisite defining element.

Actually "the reason TTL was designed for 5 volts BCC"
was the requisite defining element. As usual, when
beaten to a logical pulp, one side attempted to shift
the goalposts.


It was nothing to do with 6.3 V AC either.
Click to expand...
Good Grief!
 
On Mon, 12 Mar 2007 14:34:47 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) Gave us:

In article <45F4CF7A.BD6428AD@hotmail.com>,
Eeyore <rabbitsfriendsandrelations@hotmail.com> wrote:
[....]
So Mr Expert. Why isn't TTL made on a 40 Volt process ?

Thats obvious. Its so there is a market for MOSFET drivers. I still want
a PIC made with Supertex's HV CMOS.
Click to expand...

Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

There would be no GHz+ Pentiums if we were still at 5 Volt logic
levels.

Getteth thyself a clue.
 
On Mon, 12 Mar 2007 15:41:36 GMT, Dan Bloomquist
<public21@lakeweb.com> Gave us:

MassiveProng wrote:

Note that TTL was the requisite defining element.

No, it is, 'Jihad needs scientists'
Click to expand...

Well, now it's:

You're a goddamned retard, as usual, BloomTARD!
 
On Mon, 12 Mar 2007 16:37:13 +0000, Eeyore
<rabbitsfriendsandrelations@hotmail.com> Gave us:

"nonsense@unsettled.com" wrote:

Dan Bloomquist wrote:

MassiveProng wrote:

Note that TTL was the requisite defining element.

Actually "the reason TTL was designed for 5 volts BCC"
was the requisite defining element. As usual, when
beaten to a logical pulp, one side attempted to shift
the goalposts.

It was nothing to do with 6.3 V AC either.
Click to expand...
The defining element for a logic voltage choice was then, is now,
and will always be SLEW RATE.
 
On Mon, 12 Mar 2007 13:04:02 -0600, "nonsense@unsettled.com"
<nonsense@unsettled.com> Gave us:

Eeyore wrote:


"nonsense@unsettled.com" wrote:


Dan Bloomquist wrote:


MassiveProng wrote:


Note that TTL was the requisite defining element.

Actually "the reason TTL was designed for 5 volts BCC"
was the requisite defining element. As usual, when
beaten to a logical pulp, one side attempted to shift
the goalposts.


It was nothing to do with 6.3 V AC either.

Good Grief!
Click to expand...

I notice you spew horseshit a lot among the posts we men are
discussing.

Are you ever going to actually attempt to post something where you
expound upon your vast knowledge? Bwuahahahah!

I think you are too wussified thinking that all the presumptions you
made over the years are going to prove to be utterly wrong.

Go ahead, boy... tell us what the truth is, so we can hit you upside
the head with our rhythm sticks!

Come on, WUSSY! Put up or shut up!
 
MassiveProng wrote:

On Mon, 12 Mar 2007 14:34:47 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) Gave us:


In article <45F4CF7A.BD6428AD@hotmail.com>,
Eeyore <rabbitsfriendsandrelations@hotmail.com> wrote:
[....]

So Mr Expert. Why isn't TTL made on a 40 Volt process ?

Thats obvious. Its so there is a market for MOSFET drivers. I still want
a PIC made with Supertex's HV CMOS.




Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.
Click to expand...
Here's a clue for you. High clock rates and complex
high density chips have a significant problem with
heat, the main reason for the ever lowering voltages
in CPU's. Long leads, the essence of distributing
heat sources, slows things down significantly.

There would be no GHz+ Pentiums if we were still at 5 Volt logic
levels.

Getteth thyself a clue.
Click to expand...
Speak to yourself, ProngHead.
 
MassiveProng wrote:

On Mon, 12 Mar 2007 16:37:13 +0000, Eeyore
rabbitsfriendsandrelations@hotmail.com> Gave us:



"nonsense@unsettled.com" wrote:


Dan Bloomquist wrote:


MassiveProng wrote:


Note that TTL was the requisite defining element.

Actually "the reason TTL was designed for 5 volts BCC"
was the requisite defining element. As usual, when
beaten to a logical pulp, one side attempted to shift
the goalposts.

It was nothing to do with 6.3 V AC either.


The defining element for a logic voltage choice was then, is now,
and will always be SLEW RATE.
Click to expand...
Here we go again. Read this and think about your statement
for a while. Preferably while wearing a dunce cap.

http://homepages.nildram.co.uk/~wylie/ICs/monolith.htm

and

http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=1421
 
In article <c55a1$45f5eebb$49ecfae$14595@DIALUPUSA.NET>,
nonsense@unsettled.com says...
MassiveProng wrote:

On Mon, 12 Mar 2007 14:34:47 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) Gave us:


In article <45F4CF7A.BD6428AD@hotmail.com>,
Eeyore <rabbitsfriendsandrelations@hotmail.com> wrote:
[....]

So Mr Expert. Why isn't TTL made on a 40 Volt process ?

Thats obvious. Its so there is a market for MOSFET drivers. I still want
a PIC made with Supertex's HV CMOS.




Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

Here's a clue for you. High clock rates and complex
high density chips have a significant problem with
heat, the main reason for the ever lowering voltages
in CPU's. Long leads, the essence of distributing
heat sources, slows things down significantly.
Click to expand...
Correct. Power is now the single limiting factor. MassivelyWrong
strikes again.
There would be no GHz+ Pentiums if we were still at 5 Volt logic
levels.

Getteth thyself a clue.

Speak to yourself, ProngHead.
Click to expand...
You have to forgive Dimbulb. He's a tad slow.

--
Keith
 
MassiveProng wrote:
On Mon, 12 Mar 2007 14:34:47 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) Gave us:


Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.
Click to expand...
Wow. Sounds like ECL is a tremendous screw up. How could it have ever
happened?

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.
Click to expand...
And all this time I thought TTL's speed bottle neck was the saturated
collector. But thanks to you, I understand that the output has to move
all the way to the 5 volt rail for true state. Thanks!

There would be no GHz+ Pentiums if we were still at 5 Volt logic
levels.
Click to expand...
And the Cray I shouldn't have existed.......
 
MassiveProng wrote:

On Mon, 12 Mar 2007 15:41:36 GMT, Dan Bloomquist
public21@lakeweb.com> Gave us:


MassiveProng wrote:

Note that TTL was the requisite defining element.

No, it is, 'Jihad needs scientists'



Well, now it's:

You're a goddamned retard, as usual, BloomTARD!
Click to expand...
As usual? What name were you trolling under at our previous encounter?
 
krw wrote:

In article <c55a1$45f5eebb$49ecfae$14595@DIALUPUSA.NET>,
nonsense@unsettled.com says...

MassiveProng wrote:


On Mon, 12 Mar 2007 14:34:47 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) Gave us:



In article <45F4CF7A.BD6428AD@hotmail.com>,
Eeyore <rabbitsfriendsandrelations@hotmail.com> wrote:
[....]


So Mr Expert. Why isn't TTL made on a 40 Volt process ?

Thats obvious. Its so there is a market for MOSFET drivers. I still want
a PIC made with Supertex's HV CMOS.




Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

Here's a clue for you. High clock rates and complex
high density chips have a significant problem with
heat, the main reason for the ever lowering voltages
in CPU's. Long leads, the essence of distributing
heat sources, slows things down significantly.


Correct. Power is now the single limiting factor. MassivelyWrong
strikes again.

There would be no GHz+ Pentiums if we were still at 5 Volt logic
levels.

Getteth thyself a clue.

Speak to yourself, ProngHead.


You have to forgive Dimbulb. He's a tad slow.
Click to expand...
And really low voltage at that.
 
In sci.physics, MassiveProng
<MassiveProng@thebarattheendoftheuniverse.org>
wrote
on Mon, 12 Mar 2007 16:52:21 -0700
<3mpbv2h1ts0jed1imfmdt5h52ukk3bcskj@4ax.com>:
On Mon, 12 Mar 2007 14:34:47 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) Gave us:

In article <45F4CF7A.BD6428AD@hotmail.com>,
Eeyore <rabbitsfriendsandrelations@hotmail.com> wrote:
[....]
So Mr Expert. Why isn't TTL made on a 40 Volt process ?

Thats obvious. Its so there is a market for MOSFET drivers. I still want
a PIC made with Supertex's HV CMOS.



Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

There would be no GHz+ Pentiums if we were still at 5 Volt logic
levels.

Getteth thyself a clue.
Click to expand...
Well, I for one was under the opinion that the reason E
= 1.2V is because P = E^2/R and also proportional to the
switching frequency of the transistors (since each switch
requires a small pulse of current; the more pulses, the
higher the power required to switch), and also proportional
to the total transistor area, which AFAIK has been largely
constant even as we pack more transistors per die.

Assuming one can run a chip at both 1.2V and 5V at the
same clock rate, the 5V running will run far hotter --
about 17.4 x more power, in fact.

Then again, there's a fair number of factors here, not the
least of which is process control. :) A chip, like an
airplane, is a bunch of compromises, one of them being
clock speed versus power dissipation. The x86 series
is an excellent example of a total bodge-up because
it compromised so many things (for example, it's still
source-code compatible with the 8080A and probably with
the Z80 as well!).

But it still works.

Now, assuming anyone wants an HV CMOS 40V logic swing, I
for one would think that the best method of achieving such
is through a 1.2V-to-40V swing converter, which presumably
would be a carefully-adjusted standard CMOS transistor-pair
inverter which flips at about 0.6 volts to ground. The rest
of the circuitry can run at 1.2 V without trouble.

If necessary the level shifter can feed another, more standard inverter.

There might be better solutions; it's been a long time since I've been
anywhere near semiconductor designs, and I only really worked with
slow-speed digital stuff at most.

--
#191, ewill3@earthlink.net
Useless C++ Programming Idea #1123133:
void f(FILE * fptr, char *p) { fgets(p, sizeof(p), fptr); }

--
Posted via a free Usenet account from http://www.teranews.com
 
Dan Bloomquist wrote:

MassiveProng wrote:
kensmith@green.rahul.net (Ken Smith) Gave us:


Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

Wow. Sounds like ECL is a tremendous screw up.
Click to expand...
ECL's use in commercial equipment is negligible.

Graham
 
"nonsense@unsettled.com" wrote:

MassiveProng wrote:
kensmith@green.rahul.net Gave us:

Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

Here's a clue for you. High clock rates and complex
high density chips have a significant problem with
heat, the main reason for the ever lowering voltages
in CPU's.
Click to expand...
*One* of the reasons. Clearly slew rate is implicated equally.

Graham
 
On Tue, 13 Mar 2007 06:29:11 +0000, Eeyore
<rabbitsfriendsandrelations@hotmail.com> Gave us:

"nonsense@unsettled.com" wrote:

MassiveProng wrote:
kensmith@green.rahul.net Gave us:

Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

Here's a clue for you. High clock rates and complex
high density chips have a significant problem with
heat, the main reason for the ever lowering voltages
in CPU's.

*One* of the reasons. Clearly slew rate is implicated equally.
Click to expand...
The transition time to an acceptable logic 1 without a false high at
5 volts is huge compared to modern logic designs. Sure power
consumption being lower is part of it, but the ability to go at 10GHz
is simply not possible at 5Volts, and certainly is at 1.2Volts.

The proof is in examining a signal. At 1.2 volts we see nice crisp,
nearly vertical slew transitions between levels. When an engineer
looks at a 5 Volt signature, he notes right away that the slew of the
pulse is so high that high frequency operation won't be possible.

I'd say reduced power consumption and heat generation was a benefit,
not the root reason for the transition.

Look at the cpu floating point wars between Intel and AMD for an
example. They are one of the main reasons that we saw this reduction
in logic level voltages (as consumers). Sure heat and power
consumption was a factor, but we would not be anywhere near where we
are if we were still at 3.3 volt logic levels on the FPUs.

So, nonsense and krw are currently on a false high for thinking that
they shot down my remarks. :-]
 
MassiveProng wrote:

Eeyore <rabbitsfriendsandrelations@hotmail.com> Gave us:
"nonsense@unsettled.com" wrote:
MassiveProng wrote:
kensmith@green.rahul.net Gave us:

Tell us, oh masterTARD, what would the maximum clock be on a 40 volt
logic swing.

Do you even know what slew rate is?

The reason it was 5 volts is because it was a reasonable voltage
that could be slewed to at a decent rate.

NOW, we are at 3.3 volts and even 1.2V. The reason is slew rate,
and the fact that we can transition much faster at those swings than
we ever could at 5V.

Here's a clue for you. High clock rates and complex
high density chips have a significant problem with
heat, the main reason for the ever lowering voltages
in CPU's.

*One* of the reasons. Clearly slew rate is implicated equally.


The transition time to an acceptable logic 1 without a false high at
5 volts is huge compared to modern logic designs. Sure power
consumption being lower is part of it, but the ability to go at 10GHz
is simply not possible at 5Volts, and certainly is at 1.2Volts.

The proof is in examining a signal. At 1.2 volts we see nice crisp,
nearly vertical slew transitions between levels. When an engineer
looks at a 5 Volt signature, he notes right away that the slew of the
pulse is so high that high frequency operation won't be possible.

I'd say reduced power consumption and heat generation was a benefit,
not the root reason for the transition.

Look at the cpu floating point wars between Intel and AMD for an
example. They are one of the main reasons that we saw this reduction
in logic level voltages (as consumers). Sure heat and power
consumption was a factor, but we would not be anywhere near where we
are if we were still at 3.3 volt logic levels on the FPUs.

So, nonsense and krw are currently on a false high for thinking that
they shot down my remarks. :-]
Click to expand...
Many answers can be found in the overclocking community.

There, they'll happily up the volts to improve slew rate (hence CPU speed). At
the expense of higher dissipation and more expensive and exotic cooling.

It's nothing but a trade off. It always has been.

What I'm surpised no-one has mentioned is load capacitance.

Graham
 
In article <3f1c7$45f554cb$4fe7735$10594@DIALUPUSA.NET>,
"nonsense@unsettled.com" <nonsense@unsettled.com> wrote:
jmfbahciv@aol.com wrote:
snip
Click to expand...

You have noted that he stripped my post to make it appear that
I was agreeing with his factoid. I was talking about something
completely different.

Happens all the time.

These are the people who when asked "What is pi" will argue to
death that it is 3.14.

# the ratio of the circumference to the diameter of a circle;
approximately equal to 3.14159265358979323846...
# private detective: someone who can be employed as a detective to
collect information
# principal investigator: the scientist in charge of an experiment or
research project
# the 16th letter of the Greek alphabet
# protease inhibitor: an antiviral drug used against HIV; interrupts HIV
replication by binding and blocking HIV protease; often used in
combination with other drugs

wordnet.princeton.edu/perl/webwn
Click to expand...
In my corner of the biz, it would have been read as priority interrupt.

/BAH
 
In article <et3pbr$rad$7@blue.rahul.net>,
kensmith@green.rahul.net (Ken Smith) wrote:
In article <et39hp$8ss_003@s948.apx1.sbo.ma.dialup.rcn.com>,
jmfbahciv@aol.com> wrote:
In article <et1957$ki3$2@blue.rahul.net>,
kensmith@green.rahul.net (Ken Smith) wrote:
In article <et0oi0$8qk_003@s776.apx1.sbo.ma.dialup.rcn.com>,
jmfbahciv@aol.com> wrote:
In article <esuqfn$ds3$5@blue.rahul.net>,
kensmith@green.rahul.net (Ken Smith) wrote:
[....]
No, you are making the same mistake over and over. As I stated before, if
you know what you are going to put into TAPE.DIR, you can make its
checksum correct. No editing of a magnetic tape was needed by the
method.

Then that TAPE.DIR was not made by taking a directory of the
tape. That was not the purpose of the file. If I had to do
it the way you suggested, I wouldn't put the file on the tape
since it would be a waste of tape space.

So now you are suddenly changing your story and saying that editing of the
tape was done.

There was no tape editing done.

In that case. The tape had to be written with the TAPE.DIR in place and
correct on the first pass.
Click to expand...
This is the point. It will never be "correct" because the file
contains a checksummed listing of itself.

<snip>

Do the exercise. Then you will see what I'm talking about.

/BAH
 
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