isolated delta-sigma converters

[Piotr Wyderski]

John Larkin wrote:

This is cool. I can hang a current shunt and a voltage divider on my
transformer output, and the isolated delta-sigma data streams can go
straight into an FPGA without an ADC.

There is a lot of delta-sigma modulators on the market. Adding a
suitable isolator brings you the same and often makes the combo
cheaper as compared to an isolated ADC. The isolator can have an
isoPower-compatible built-in transformer driver, which solves your
second problem as well. SOme of the modulators have Manchester output,
which allows transformer-based data link isolation and you basically end
up with just two tiny toroidal cores next to the chip.

And when you have an isolator and a power supply, then why delta-sigma,
if LTC1407A-1 is so cute?

Best regards, Piotr

 

[John Larkin]

On Mon, 17 Jun 2019 09:10:57 +0200, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

Winfield Hill wrote:

Yes it's cool.

78kSPS, ENOB of 14. Yawn.
LTC1407A-1 is a 14-bit 1.5MSPS part, so decimating it by
19 to match the delta-sigma slug would bring you a tad above
2 more bits of processing gain. And you can use the fast
bitstream for overcurrent/overvoltage protection purposes.
The delta-sigma would be fast enough to report the primary side
destruction, if you are lucky. and the SAR is dual/simultaneous
sampling, so you can measure current and voltage with the same part.
I use exactly this configuration in another project for mains
synchronization and I'm planning to use it as well in a bridgeless
totem-pole PFC.

John already has an FPGA around there, so the deserialization of
the "high speed" 51MHz bitstream would be another exciting task, yawn.

Best regards, Piotr

Both the ADI and TI parts do delta-sigma at 20 MHz. It is cool that we
could have different lowpass filters in the FPGA for different
purposes, trade off resolution for speed as needed.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[John Larkin]

On Mon, 17 Jun 2019 08:54:19 +0200, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

John Larkin wrote:

This is cool. I can hang a current shunt and a voltage divider on my
transformer output, and the isolated delta-sigma data streams can go
straight into an FPGA without an ADC.

There is a lot of delta-sigma modulators on the market. Adding a
suitable isolator brings you the same and often makes the combo
cheaper as compared to an isolated ADC. The isolator can have an
isoPower-compatible built-in transformer driver, which solves your
second problem as well. SOme of the modulators have Manchester output,
which allows transformer-based data link isolation and you basically end
up with just two tiny toroidal cores next to the chip.

And when you have an isolator and a power supply, then why delta-sigma,
if LTC1407A-1 is so cute?

Best regards, Piotr

That is interesting. It's only 12 bits, and we'd have to gain up and
maybe range switch our current shunt voltage. And add some common-mode
input voltage to handle our bipolar sine waves.

About a wash.



--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[boB]

On Mon, 17 Jun 2019 06:39:56 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Mon, 17 Jun 2019 09:10:57 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

Winfield Hill wrote:

Yes it's cool.

78kSPS, ENOB of 14. Yawn.
LTC1407A-1 is a 14-bit 1.5MSPS part, so decimating it by
19 to match the delta-sigma slug would bring you a tad above
2 more bits of processing gain. And you can use the fast
bitstream for overcurrent/overvoltage protection purposes.
The delta-sigma would be fast enough to report the primary side
destruction, if you are lucky. and the SAR is dual/simultaneous
sampling, so you can measure current and voltage with the same part.
I use exactly this configuration in another project for mains
synchronization and I'm planning to use it as well in a bridgeless
totem-pole PFC.

John already has an FPGA around there, so the deserialization of
the "high speed" 51MHz bitstream would be another exciting task, yawn.

Best regards, Piotr

Both the ADI and TI parts do delta-sigma at 20 MHz. It is cool that we
could have different lowpass filters in the FPGA for different
purposes, trade off resolution for speed as needed.

What I like about Delta sigma A/Ds is that you only have to have a
-3dB RC filter on the front end instead of a high order sharp filter.

Same thing I believe for the oversampling D/A converters.

 

[Lasse Langwadt Christense]

mandag den 17. juni 2019 kl. 23.04.47 UTC+2 skrev boB:

On Mon, 17 Jun 2019 06:39:56 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Mon, 17 Jun 2019 09:10:57 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

Winfield Hill wrote:

Yes it's cool.

78kSPS, ENOB of 14. Yawn.
LTC1407A-1 is a 14-bit 1.5MSPS part, so decimating it by
19 to match the delta-sigma slug would bring you a tad above
2 more bits of processing gain. And you can use the fast
bitstream for overcurrent/overvoltage protection purposes.
The delta-sigma would be fast enough to report the primary side
destruction, if you are lucky. and the SAR is dual/simultaneous
sampling, so you can measure current and voltage with the same part.
I use exactly this configuration in another project for mains
synchronization and I'm planning to use it as well in a bridgeless
totem-pole PFC.

John already has an FPGA around there, so the deserialization of
the "high speed" 51MHz bitstream would be another exciting task, yawn.

Best regards, Piotr

Both the ADI and TI parts do delta-sigma at 20 MHz. It is cool that we
could have different lowpass filters in the FPGA for different
purposes, trade off resolution for speed as needed.


What I like about Delta sigma A/Ds is that you only have to have a
-3dB RC filter on the front end instead of a high order sharp filter.

Same thing I believe for the oversampling D/A converters.

Delta-sigma basically work the same in both directions

 

[John Larkin]

On Mon, 17 Jun 2019 14:04:45 -0700, boB <boB@K7IQ.com> wrote:

On Mon, 17 Jun 2019 06:39:56 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Mon, 17 Jun 2019 09:10:57 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

Winfield Hill wrote:

Yes it's cool.

78kSPS, ENOB of 14. Yawn.
LTC1407A-1 is a 14-bit 1.5MSPS part, so decimating it by
19 to match the delta-sigma slug would bring you a tad above
2 more bits of processing gain. And you can use the fast
bitstream for overcurrent/overvoltage protection purposes.
The delta-sigma would be fast enough to report the primary side
destruction, if you are lucky. and the SAR is dual/simultaneous
sampling, so you can measure current and voltage with the same part.
I use exactly this configuration in another project for mains
synchronization and I'm planning to use it as well in a bridgeless
totem-pole PFC.

John already has an FPGA around there, so the deserialization of
the "high speed" 51MHz bitstream would be another exciting task, yawn.

Best regards, Piotr

Both the ADI and TI parts do delta-sigma at 20 MHz. It is cool that we
could have different lowpass filters in the FPGA for different
purposes, trade off resolution for speed as needed.


What I like about Delta sigma A/Ds is that you only have to have a
-3dB RC filter on the front end instead of a high order sharp filter.

Same thing I believe for the oversampling D/A converters.

We use a 20-bit delta-sigma DAC, the DAC1220. It's awesome.

It includes the output filter; all we do is supply two caps.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Lasse Langwadt Christense]

mandag den 17. juni 2019 kl. 15.40.05 UTC+2 skrev John Larkin:

On Mon, 17 Jun 2019 09:10:57 +0200, Piotr Wyderski
peter.pan@neverland.mil> wrote:

Winfield Hill wrote:

Yes it's cool.

78kSPS, ENOB of 14. Yawn.
LTC1407A-1 is a 14-bit 1.5MSPS part, so decimating it by
19 to match the delta-sigma slug would bring you a tad above
2 more bits of processing gain. And you can use the fast
bitstream for overcurrent/overvoltage protection purposes.
The delta-sigma would be fast enough to report the primary side
destruction, if you are lucky. and the SAR is dual/simultaneous
sampling, so you can measure current and voltage with the same part.
I use exactly this configuration in another project for mains
synchronization and I'm planning to use it as well in a bridgeless
totem-pole PFC.

John already has an FPGA around there, so the deserialization of
the "high speed" 51MHz bitstream would be another exciting task, yawn.

Best regards, Piotr

Both the ADI and TI parts do delta-sigma at 20 MHz. It is cool that we
could have different lowpass filters in the FPGA for different
purposes, trade off resolution for speed as needed.

don't forget the delay in the lowpass filter needed, it might get tricky
when you try to close the loop

 

[Piotr Wyderski]

John Larkin wrote:

> Both the ADI and TI parts do delta-sigma at 20 MHz.

20MHz is the bitstream rate, but you need some time for the slug to
crawl up. Actually, 256 cycles for a decent resolution. A SAR provides
the result in a single shot.

It is cool that we
could have different lowpass filters in the FPGA for different
purposes, trade off resolution for speed as needed.

It is exactly the same with any other ADC architecture. The magic of
decimation and processing gain.

The high-speed 1.5MSPS SAR output is used for range checking,
its decimated by 4 variant feeds a PLL, further decimated by
15 is used for some phasor analytics (@25kSPS and about 17 ENOB).

Best regards, Piotr

 

[Piotr Wyderski]

John Larkin wrote:

> We use a 20-bit delta-sigma DAC, the DAC1220. It's awesome.

MAX5719?

Best regards, Piotr

 

[Piotr Wyderski]

John Larkin wrote:

> That is interesting. It's only 12 bits

No, it is the braindead LTC naming convention. Only IXYS outruns them
with their habit to use the output of MD5 for their part names, I believe.

1407 is 12 bit unsigned, 1407-1 is 14 bit unsigned, 1407A is 12 bit but
signed and 1407A-1 is signed 14 bit. Go and hit them with something
heavy, if you please.

> And add some common-mode input voltage to handle our bipolar sine waves.

It has a decent internal 2.5V reference and the input stage is
differential, so it would be straightforward.

Best regards, Piotr

 

On Tue, 18 Jun 2019 01:17:36 +0200, Piotr Wyderski
<peter.pan@neverland.mil> wrote:

John Larkin wrote:

Both the ADI and TI parts do delta-sigma at 20 MHz.

20MHz is the bitstream rate, but you need some time for the slug to
crawl up. Actually, 256 cycles for a decent resolution. A SAR provides
the result in a single shot.

Single shot? An SAR requires a clock for each bit. Did you mean a
flash converter? Good luck with a 20bit flash converter. ;-)

 

[Piotr Wyderski]

krw@notreal.com wrote:

> Single shot? An SAR requires a clock for each bit.

I meant a single transmission burst, not the slow accumulation process
in the reconstruction filter. Send 34 pulses and you have your two
14-bit results sitting in a shift register. You can have up to 1.5e6
such bursts per second in this particular case, which allows for ~700ns
response time to an event.

Best regards, Piotr