ISE v9 VHDL compilation

[Mark McDougall]

Hi,

I'm a regular Quartus user who occasionally uses ISE to compile the same
code. Just today I attempted to compile code that has been working in
Quartus for several years now. However, I've run into several compilation
errors which have left me scratching my head.

Stupid stuff like "unconstrained arrays" which clearly are constrained.
Granted, I'm using the 'left attribute on a std_logic_vector whose range
is specified in a generic, but Quartus doesn't have any problem with it.

Just wondering if anyone else here does cross-vendor work and finds ISE
similarly frustrating to work with???

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Mike Treseler]

Mark McDougall wrote:

Just wondering if anyone else here does cross-vendor work and finds ISE
similarly frustrating to work with???

Yes.
It is annoying to have to defile my code for ise.
Just submit the bug report.
They'll get it sorted out eventually.

Or better yet, they might take the easy way out
and switch to a verific front end like brand A.
and many others.

-- Mike Treseler

 

[beky4kr@gmail.com]

On 21 נובמבר, 02:53, Mike Treseler <mtrese...@gmail.com> wrote:

Mark McDougall wrote:
Just wondering if anyone else here does cross-vendor work and finds ISE
similarly frustrating to work with???

Yes.
It is annoying to have to defile my code for ise.
Just submit the bug report.
They'll get it sorted out eventually.

Or better yet, they might take the easy way out
and switch to a verific front end like brand A.
and many others.

-- Mike Treseler

You may want to see xilinx ise script examples at:
h--p://bknpk.no-ip.biz/leon_i2c_syn/leon_i2c_syn.html
h--p://bknpk.no-ip.biz/usb_8051_verilog_syn/usb_1_syn_intro.html

 

[Eric Smith]

Mike Treseler wrote about VHDL support in Xilinx ISE (XST):

Or better yet, they might take the easy way out
and switch to a verific front end like brand A.
and many others.

The front page of the Verific web site shows that Xilinx
is already one of their customers, using it for ISIM!

 

[Mike Treseler]

Eric Smith wrote:

The front page of the Verific web site shows that Xilinx
is already one of their customers, using it for ISIM!

That is good news.
I hope the isim group will
have a talk with the synthesis group.

-- Mike Treseler

 

[Allan Herriman]

Mike Treseler <mtreseler@gmail.com> wrote in news:49272382.4010202
@gmail.com:

Eric Smith wrote:

The front page of the Verific web site shows that Xilinx
is already one of their customers, using it for ISIM!

That is good news.
I hope the isim group will
have a talk with the synthesis group.

-- Mike Treseler

Verific claim compliance with IEEE 1076-1993

Someone should email a copy of VHDL-2008 to Verific. Or perhaps VHDL-
2006. Or maybe even VHDL-2001.

I really hope this is just out of date information on their web site.

One of the advantages of a monoculture is that the implementation of the
language(s) will be consistent across all the tools.
One of the disadvantages is that the one company wields a lot of power in
terms of the direction of the language(s), more even than the standards
bodies.

Regards,
Allan

 

[RedskullDC]

Hi Mark,

"Mark McDougall" <markm@vl.com.au> wrote in message
news:4925fe49$1@dnews.tpgi.com.au...

Hi,

I'm a regular Quartus user who occasionally uses ISE to compile the same
code. Just today I attempted to compile code that has been working in
Quartus for several years now. However, I've run into several compilation
errors which have left me scratching my head.

Stupid stuff like "unconstrained arrays" which clearly are constrained.
Granted, I'm using the 'left attribute on a std_logic_vector whose range
is specified in a generic, but Quartus doesn't have any problem with it.

Just wondering if anyone else here does cross-vendor work and finds ISE
similarly frustrating to work with???

Or this snippet from your trs80/m1/platform.vhd for example:

....
clock_a => clk_video,
address_a => tilemap_i.map_a(9 downto 0),
wren_a => '0',
data_a => (others => 'X'), -- ISE complains about "others" being
"non-specific" array
q_a => tilemap_o.map_d(7 downto 0)
);

That was using 10.1.3 incidentally.

Sure you have plenty of other ISE horror stories to tell....

Cheers,
Leslie