J
JJ
Guest
fpga_toys@yahoo.com wrote:
snipping, kind of tired of being told software taking over hardware
design, it ain't
interesting content problems, I suspect it's already too late for new
comers without strong EE backgrounds or associates.
15 years ago FPGAs were pretty darn simple and not much use for
anything but glue logic. Good ole days when any old CMOS logic slapped
together just worked. Synthesis just around the corner.
10 years ago they got big enough but not performance enough to start to
make predictions about RC and the possibly of replacement of general
purpose cpus with hardware computing ie the 4000 days and a couple of
new companies to boot. ASIC design started to get harder.
5 years ago with Virtex I'd say they started to get the ASIC
performance with the embedded blocks and specialized IO resources
making performance almost even to cover the much slower LUT blocks, and
we also got the hugely more complex data sheets.
Today most FPGAs seem to have the whole kitchen sink in there to make
complex systems more practical if the sink can be made small enough to
hide cost when not used.
Look at any data sheet for modern parts, maybe 5% or less could be
understood by your avg SW engineer (far less I bet), the rest is all
electrical stuff, signal integrity, power supplies, packaging,
reliabilty, clocking in no particular order.
Ask around here for books on FPGA computing, there aren't any, there
all old shit 10yrs or more from the easy days. I have one that covers
the 3000 series. Ray has one coming and it sure ain't targeted at
software guys, he's too busy with real work, as are most EEs with a job
to write up their current knowledge. FPGAs are simply moving too fast
to be documented for the laissez faire user.
SW engineers with the mathematical applications are used to dealing
with ready made PC boxen, give enough ventilation and hot math
shouldn't faze a P4. There really isn't anything available in the same
sense of off the shelf FPGA computing that can be sold as a std board
to all the math, idea guys with out HW pain. Yeh there are lots of FPGA
PCI cards but they are mostly not useable to software guys without some
EE around as well as hardware lab tools. So that means a special
application likely needs special boards to be built. Welcome to the
real world, power supplies, interfaces, SI, GHz IO's, lead free. They
haven't tought that in school in CS ever, and perhaps maybe some EE
schools too. I can feel pretty sure that EEs that don't know this won't
get much work. I suspect logic classes are going to be with us too for
ever.
When I interviewed candidates that don't know basic bool algebra but
would like to do mil gate designs, I'd say let you know later, or let
them know what they need to know. Is that job protection, sure it is,
EEs don't want Joe90 liability around, bad ASIC design kills companies.
We are going the same place with FPGA systems, bad designs will never
work but only the project is lost, not million $ mask sets. My last
employer's FPGA project cost far more than previous predecessor full
custom mixed signal ASIC, it had lots of nice new math in it to figure
out. Even really good EEs make logic mistakes, so some further
abstractions are likely but that doesn't help much with all the dirty
backend EE stuff.
of SW engineers coming to the FPGA party are already over. FPGAs are
getting bigger and more interesting but a darn site harder to use and
that won't ever get covered up by synthesis tools.
Also from what I have seen of some of the applications of FPGAs to
computing v PC computing, the FPGA projest didn't even match the PC
solution on cost. Not because the FPAG doesn't have the grunt but
because too much was left on the table since the design was done by
math oriented people. Now as I said before cpu designers have decided
to go the same way FPGA are, packing density plus any incremental clock
speed so its a parallel race again. My gut tells me that PC computing
is still the best way to go if a plain C description works using 32 bit
int math and esp FP math. But when the math looks like crypto with S
boxes and shuffles or has dedicated IO interface, FPGAs cream all over.
Multi disciplined teams are the future but EEs won't be in the back
seat.
I am done
John Jakson
transputer guy
Marlboro MA
BTW I don't know how to change brake pads or do oil changes (or even
spell) so none of the above makes diddly squat.
snipping, kind of tired of being told software taking over hardware
design, it ain't
While thats likely somewhat true and I really welcome anyone with
interesting content problems, I suspect it's already too late for new
comers without strong EE backgrounds or associates.
15 years ago FPGAs were pretty darn simple and not much use for
anything but glue logic. Good ole days when any old CMOS logic slapped
together just worked. Synthesis just around the corner.
10 years ago they got big enough but not performance enough to start to
make predictions about RC and the possibly of replacement of general
purpose cpus with hardware computing ie the 4000 days and a couple of
new companies to boot. ASIC design started to get harder.
5 years ago with Virtex I'd say they started to get the ASIC
performance with the embedded blocks and specialized IO resources
making performance almost even to cover the much slower LUT blocks, and
we also got the hugely more complex data sheets.
Today most FPGAs seem to have the whole kitchen sink in there to make
complex systems more practical if the sink can be made small enough to
hide cost when not used.
Look at any data sheet for modern parts, maybe 5% or less could be
understood by your avg SW engineer (far less I bet), the rest is all
electrical stuff, signal integrity, power supplies, packaging,
reliabilty, clocking in no particular order.
Ask around here for books on FPGA computing, there aren't any, there
all old shit 10yrs or more from the easy days. I have one that covers
the 3000 series. Ray has one coming and it sure ain't targeted at
software guys, he's too busy with real work, as are most EEs with a job
to write up their current knowledge. FPGAs are simply moving too fast
to be documented for the laissez faire user.
SW engineers with the mathematical applications are used to dealing
with ready made PC boxen, give enough ventilation and hot math
shouldn't faze a P4. There really isn't anything available in the same
sense of off the shelf FPGA computing that can be sold as a std board
to all the math, idea guys with out HW pain. Yeh there are lots of FPGA
PCI cards but they are mostly not useable to software guys without some
EE around as well as hardware lab tools. So that means a special
application likely needs special boards to be built. Welcome to the
real world, power supplies, interfaces, SI, GHz IO's, lead free. They
haven't tought that in school in CS ever, and perhaps maybe some EE
schools too. I can feel pretty sure that EEs that don't know this won't
get much work. I suspect logic classes are going to be with us too for
ever.
When I interviewed candidates that don't know basic bool algebra but
would like to do mil gate designs, I'd say let you know later, or let
them know what they need to know. Is that job protection, sure it is,
EEs don't want Joe90 liability around, bad ASIC design kills companies.
We are going the same place with FPGA systems, bad designs will never
work but only the project is lost, not million $ mask sets. My last
employer's FPGA project cost far more than previous predecessor full
custom mixed signal ASIC, it had lots of nice new math in it to figure
out. Even really good EEs make logic mistakes, so some further
abstractions are likely but that doesn't help much with all the dirty
backend EE stuff.
they seem to be pretty coy about what they are upto. I suspect the days
of SW engineers coming to the FPGA party are already over. FPGAs are
getting bigger and more interesting but a darn site harder to use and
that won't ever get covered up by synthesis tools.
Also from what I have seen of some of the applications of FPGAs to
computing v PC computing, the FPGA projest didn't even match the PC
solution on cost. Not because the FPAG doesn't have the grunt but
because too much was left on the table since the design was done by
math oriented people. Now as I said before cpu designers have decided
to go the same way FPGA are, packing density plus any incremental clock
speed so its a parallel race again. My gut tells me that PC computing
is still the best way to go if a plain C description works using 32 bit
int math and esp FP math. But when the math looks like crypto with S
boxes and shuffles or has dedicated IO interface, FPGAs cream all over.
Multi disciplined teams are the future but EEs won't be in the back
seat.
I am done
John Jakson
transputer guy
Marlboro MA
BTW I don't know how to change brake pads or do oil changes (or even
spell) so none of the above makes diddly squat.