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On Wednesday, June 14, 2023 at 1:06:37?PM UTC-4, John Larkin wrote:
On Tue, 13 Jun 2023 13:04:09 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
32768 Hz is not \"fast\" in any sense. The energy used in digital logic is due to charging and discharging the capacitance of the circuit elements.
P = 1/2 C F V^2, where P is power, C is capacitance, F is frequency and V is voltage.
C F V^2. Both edges burn power.
Two other fine points: C for a gate is proportional to its output current limit, so less current
means you can design low-C transistors that burn less power. Clocking a flipflop (ripple or
synchronous counter) has a strict dV/dt requirement (CD4013 max rise time 10 us at 5V),
so lower current inputs don\'t suffice to drive it as a divider; watches use different CMOS.
Also, this is about driving a capacitive load, i.e. an electrostatic motor, where there\'s
a torque because rotation raises the capacitance of the most-charged stator elements.
That \"C\" in the formula isn\'t a constant for this case.
On Wednesday, June 14, 2023 at 1:06:37â¯PM UTC-4, John Larkin wrote:
On Tue, 13 Jun 2023 13:04:09 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
32768 Hz is not \"fast\" in any sense. The energy used in digital logic is due to charging and discharging the capacitance of the circuit elements.
P = 1/2 C F V^2, where P is power, C is capacitance, F is frequency and V is voltage.
C F V^2. Both edges burn power.
Two other fine points: C for a gate is proportional to its output current limit, so less current
means you can design low-C transistors that burn less power. Clocking a flipflop (ripple or
synchronous counter) has a strict dV/dt requirement (CD4013 max rise time 10 us at 5V),
so lower current inputs don\'t suffice to drive it as a divider; watches use different CMOS.
Also, this is about driving a capacitive load, i.e. an electrostatic motor, where there\'s
a torque because rotation raises the capacitance of the most-charged stator elements.
That \"C\" in the formula isn\'t a constant for this case.
On Tue, 13 Jun 2023 13:04:09 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Tuesday, June 13, 2023 at 2:57:42?PM UTC-4, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34?PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55?AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a 32727 Hz quartz
crystal with pseudorandom division, rather than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared to strictly internal logic. If you are trying to design your own clock drive, I don\'t think you will do better on power than using a standard CMOS clock chip. In any event, the focus should be on the oscillator, rather than the divider.
Perhaps we have reached the X/Y point. You asked about X, but what is Y? What are you really trying to do?
I was advised that one high-end watch uses an electrostatic motor to drive the (sweep?) second
hand, but an electromagnetic (solenoid/ratchet?) drive for minutes. The claim was lower
energy use, allowing energy-harvesting to suffice.
I think it\'s this one:
https://www.digitaltrends.com/mobile/the-story-of-accutron-dna-world-first-twin-turbine-electrostatic-watch/
... and it got me thinking about the wasteful high-current-for-fast-slew clocking requirements of a flipflop.
32768 Hz is not \"fast\" in any sense. The energy used in digital logic is due to charging and discharging the capacitance of the circuit elements.
P = 1/2 C F V^2, where P is power, C is capacitance, F is frequency and V is voltage.
C F V^2. Both edges burn power.
On Wed, 14 Jun 2023 11:38:33 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Wednesday, June 14, 2023 at 1:06:37?PM UTC-4, John Larkin wrote:
On Tue, 13 Jun 2023 13:04:09 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
32768 Hz is not \"fast\" in any sense. The energy used in digital logic is due to charging and discharging the capacitance of the circuit elements..
P = 1/2 C F V^2, where P is power, C is capacitance, F is frequency and V is voltage.
C F V^2. Both edges burn power.
Two other fine points: C for a gate is proportional to its output current limit, so less current
means you can design low-C transistors that burn less power. Clocking a flipflop (ripple or
synchronous counter) has a strict dV/dt requirement (CD4013 max rise time 10 us at 5V),
so lower current inputs don\'t suffice to drive it as a divider; watches use different CMOS.
Also, this is about driving a capacitive load, i.e. an electrostatic motor, where there\'s
a torque because rotation raises the capacitance of the most-charged stator elements.
That \"C\" in the formula isn\'t a constant for this case.
C may not be literal capacitance, but shoot-through current
equivalent.
On Wednesday, June 14, 2023 at 8:31:33?AM UTC-4, Martin Brown wrote:
On 13/06/2023 19:57, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34?PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55?AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a 32727 Hz quartz
crystal with pseudorandom division, rather than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared to strictly internal logic. If you are trying to design your own clock drive, I don\'t think you will do better on power than using a standard CMOS clock chip. In any event, the focus should be on the oscillator, rather than the divider.
Perhaps we have reached the X/Y point. You asked about X, but what is Y? What are you really trying to do?
The trick in coding a precision timepiece from a low speed clock is to
be able to divide by 32768 +/-a few so that the crystal doesn\'t have to
be trimmed at all. You merely have the thing self calibrate its divisor
off an external precision 1s reference pulse.
The \"trick\"? Adjusting the divisor is a common \"trick\", but with poor results. 1 part in 32,768 is about 30 ppm which gives an error of 2.6 secs per day and 1.3 minutes per month. Most consider this not acceptable. Digital trimming requires a different circuit than a simple divider, something that will use significantly more power, like an NCO.
On Wed, 14 Jun 2023 09:28:56 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Wednesday, June 14, 2023 at 8:31:33?AM UTC-4, Martin Brown wrote:
On 13/06/2023 19:57, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34?PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55?AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a 32727 Hz quartz
crystal with pseudorandom division, rather than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared to strictly internal logic. If you are trying to design your own clock drive, I don\'t think you will do better on power than using a standard CMOS clock chip. In any event, the focus should be on the oscillator, rather than the divider.
The trick in coding a precision timepiece from a low speed clock is to
be able to divide by 32768 +/-a few so that the crystal doesn\'t have to
be trimmed at all. You merely have the thing self calibrate its divisor
off an external precision 1s reference pulse.
The \"trick\"? Adjusting the divisor is a common \"trick\", but with poor results. 1 part in 32,768 is about 30 ppm which gives an error of 2.6 secs per day and 1.3 minutes per month. Most consider this not acceptable. Digital trimming requires a different circuit than a simple divider, something that will use significantly more power, like an NCO.
If this clock is intended for human consumption, why bother to keep
_exactly_ on time all the time. 30 ppm is about 0.1 s in one hour and
the error increases to a full second in 10 hours.
Use a crystal that is always above nominal frequency and just say
about every 10 hours, inhibit a single \"1 s\" pulse from the second
hand motor.
On Wednesday, June 14, 2023 at 8:31:33â¯AM UTC-4, Martin Brown wrote:
On 13/06/2023 19:57, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34â¯PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55â¯AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a
32727 Hz quartz crystal with pseudorandom division, rather
than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared
to strictly internal logic. If you are trying to design your
own clock drive, I don\'t think you will do better on power than
using a standard CMOS clock chip. In any event, the focus
should be on the oscillator, rather than the divider.
Perhaps we have reached the X/Y point. You asked about X, but
what is Y? What are you really trying to do?
The trick in coding a precision timepiece from a low speed clock is
to be able to divide by 32768 +/-a few so that the crystal doesn\'t
have to be trimmed at all. You merely have the thing self calibrate
its divisor off an external precision 1s reference pulse.
The \"trick\"? Adjusting the divisor is a common \"trick\", but with
poor results. 1 part in 32,768 is about 30 ppm which gives an error
of 2.6 secs per day and 1.3 minutes per month. Most consider this
not acceptable. Digital trimming requires a different circuit than a
simple divider, something that will use significantly more power,
like an NCO.
I was advised that one high-end watch uses an electrostatic motor
to drive the (sweep?) second hand, but an electromagnetic
(solenoid/ratchet?) drive for minutes. The claim was lower energy
use, allowing energy-harvesting to suffice. I think it\'s this
one:
https://www.digitaltrends.com/mobile/the-story-of-accutron-dna-world-first-twin-turbine-electrostatic-watch/
That looks to me like 100% marketing BS. Anything that moves quickly
will have air resistance and bearing friction to contend with.
Air resistance??? You are making an assumption of relative power
losses.
On Thursday, June 15, 2023 at 3:27:18â¯AM UTC-7, upsid...@downunder.com wrote:
On Wed, 14 Jun 2023 09:28:56 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Wednesday, June 14, 2023 at 8:31:33?AM UTC-4, Martin Brown wrote:
On 13/06/2023 19:57, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34?PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55?AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a 32727 Hz quartz
crystal with pseudorandom division, rather than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared to strictly internal logic. If you are trying to design your own clock drive, I don\'t think you will do better on power than using a standard CMOS clock chip. In any event, the focus should be on the oscillator, rather than the divider.
The trick in coding a precision timepiece from a low speed clock is to
be able to divide by 32768 +/-a few so that the crystal doesn\'t have to
be trimmed at all. You merely have the thing self calibrate its divisor
off an external precision 1s reference pulse.
The \"trick\"? Adjusting the divisor is a common \"trick\", but with poor results. 1 part in 32,768 is about 30 ppm which gives an error of 2.6 secs per day and 1.3 minutes per month. Most consider this not acceptable. Digital trimming requires a different circuit than a simple divider, something that will use significantly more power, like an NCO.
The implementation of divide-by-16/17 is relatively trivial, and a Bresenham application
can dither so, and calibrate any reasonably-close frequency to a standard..
Pulse swallowing is not hard, and the result won\'t have to exceed a millisecond.
If this clock is intended for human consumption, why bother to keep
_exactly_ on time all the time. 30 ppm is about 0.1 s in one hour and
the error increases to a full second in 10 hours.
Use a crystal that is always above nominal frequency and just say
about every 10 hours, inhibit a single \"1 s\" pulse from the second
hand motor.
The item in question, though, has a sweep second hand with NO jerky motion,
and a minute hand that never points at fractional minutes... a catch-up correction
would be jarring to the user (and it\'s a pricey item, this watch). One would want the
calibration correction high up the divider chain, to manage the smooth second hand.
On 14/06/2023 17:28, Ricky wrote:
On Wednesday, June 14, 2023 at 8:31:33â¯AM UTC-4, Martin Brown wrote:
On 13/06/2023 19:57, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34â¯PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55â¯AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a
32727 Hz quartz crystal with pseudorandom division, rather
than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared
to strictly internal logic. If you are trying to design your
own clock drive, I don\'t think you will do better on power than
using a standard CMOS clock chip. In any event, the focus
should be on the oscillator, rather than the divider.
Perhaps we have reached the X/Y point. You asked about X, but
what is Y? What are you really trying to do?
The trick in coding a precision timepiece from a low speed clock is
to be able to divide by 32768 +/-a few so that the crystal doesn\'t
have to be trimmed at all. You merely have the thing self calibrate
its divisor off an external precision 1s reference pulse.
The \"trick\"? Adjusting the divisor is a common \"trick\", but with
poor results. 1 part in 32,768 is about 30 ppm which gives an error
of 2.6 secs per day and 1.3 minutes per month. Most consider this
not acceptable. Digital trimming requires a different circuit than a
simple divider, something that will use significantly more power,
like an NCO.
The real trick is to divide by the right amount when averaged over a day
so that the long term accuracy is around 1ppm but still subject to
thermal drift. The effective divisor is fractional.
You don\'t just pick a single divisor you dither between a pair of them
in such a way that it is virtually exact when averaged over a day.
You only need to represent fractional steps of N/32 to get 1ppm. Phase
noise is a bit rubbish but you generally don\'t care in a timepiece.
I was advised that one high-end watch uses an electrostatic motor
to drive the (sweep?) second hand, but an electromagnetic
(solenoid/ratchet?) drive for minutes. The claim was lower energy
use, allowing energy-harvesting to suffice. I think it\'s this
one:
https://www.digitaltrends.com/mobile/the-story-of-accutron-dna-world-first-twin-turbine-electrostatic-watch/
That looks to me like 100% marketing BS. Anything that moves quickly
will have air resistance and bearing friction to contend with.
Air resistance??? You are making an assumption of relative power
losses.
Fast spinning disk close to other non moving parts but with air in
between. Boundary layers are invariably bad news friction wise.
On Wed, 14 Jun 2023 11:38:33 -0700 (PDT), whit3rd <whi...@gmail.com
wrote:
On Wednesday, June 14, 2023 at 1:06:37?PM UTC-4, John Larkin wrote:
On Tue, 13 Jun 2023 13:04:09 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
32768 Hz is not \"fast\" in any sense. The energy used in digital logic is due to charging and discharging the capacitance of the circuit elements..
P = 1/2 C F V^2, where P is power, C is capacitance, F is frequency and V is voltage.
C F V^2. Both edges burn power.
Two other fine points: C for a gate is proportional to its output current limit, so less current
means you can design low-C transistors that burn less power. Clocking a flipflop (ripple or
synchronous counter) has a strict dV/dt requirement (CD4013 max rise time 10 us at 5V),
so lower current inputs don\'t suffice to drive it as a divider; watches use different CMOS.
Also, this is about driving a capacitive load, i.e. an electrostatic motor, where there\'s
a torque because rotation raises the capacitance of the most-charged stator elements.
That \"C\" in the formula isn\'t a constant for this case.
C may not be literal capacitance, but shoot-through current
equivalent.
On Thursday, June 15, 2023 at 3:27:18â¯AM UTC-7, upsid...@downunder.com wrote:
On Wed, 14 Jun 2023 09:28:56 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Wednesday, June 14, 2023 at 8:31:33?AM UTC-4, Martin Brown wrote:
On 13/06/2023 19:57, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34?PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55?AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a 32727 Hz quartz
crystal with pseudorandom division, rather than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared to strictly internal logic. If you are trying to design your own clock drive, I don\'t think you will do better on power than using a standard CMOS clock chip. In any event, the focus should be on the oscillator, rather than the divider.
The trick in coding a precision timepiece from a low speed clock is to
be able to divide by 32768 +/-a few so that the crystal doesn\'t have to
be trimmed at all. You merely have the thing self calibrate its divisor
off an external precision 1s reference pulse.
The \"trick\"? Adjusting the divisor is a common \"trick\", but with poor results. 1 part in 32,768 is about 30 ppm which gives an error of 2.6 secs per day and 1.3 minutes per month. Most consider this not acceptable. Digital trimming requires a different circuit than a simple divider, something that will use significantly more power, like an NCO.
The implementation of divide-by-16/17 is relatively trivial, and a Bresenham application
can dither so, and calibrate any reasonably-close frequency to a standard.
Pulse swallowing is not hard, and the result won\'t have to exceed a millisecond.
If this clock is intended for human consumption, why bother to keep
_exactly_ on time all the time. 30 ppm is about 0.1 s in one hour and
the error increases to a full second in 10 hours.
Use a crystal that is always above nominal frequency and just say
about every 10 hours, inhibit a single \"1 s\" pulse from the second
hand motor.
and a minute hand that never points at fractional minutes... a catch-up correction
would be jarring to the user (and it\'s a pricey item, this watch). One would want the
calibration correction high up the divider chain, to manage the smooth second hand.
On 15/06/2023 13:33, whit3rd wrote:
On Thursday, June 15, 2023 at 3:27:18â¯AM UTC-7, upsid...@downunder.com wrote:
Use a crystal that is always above nominal frequency and just say
about every 10 hours, inhibit a single \"1 s\" pulse from the second
hand motor.
That\'s a bit clunky.
There is no reason to let the thing be out by more than a fraction of a
ms - CMOS logic doesn\'t use much power at all at these slow speeds. It
even needs a series resistor to stop the CMOS drive damaging the Xtal.
The item in question, though, has a sweep second hand with NO jerky motion,
That only means that the motion appears smooth to the human eye - that
isn\'t so difficult to achieve 600 steps around the circle instead of 60
would be more than adequate. Rolex get away with 480.
and a minute hand that never points at fractional minutes... a catch-up correction
would be jarring to the user (and it\'s a pricey item, this watch). One would want the
calibration correction high up the divider chain, to manage the smooth second hand.
It doesn\'t have to be very far up the correction chain - human eye
cannot reliably distinguish events closer than 0.1s reliably. Even
trained observers can\'t click a button when they see an event better
than that. A video camera manages 25 fps (or 30 in the USA).
If you video the \"smooth\" motion particularly with a faster than real
life frame rate (aka in slow motion) I expect you will see that it is
not smooth at all - merely stepping faster than the eye can see.
It is the main difference between a real Rolex and a copy watch (which
you could be forgiven for thinking was the local greeting in Hong Kong).
ISTR they typically use 8Hz as the stepper frequency to look smooth.
A 1s error is pretty easy to spot though.
In binary ripple counters, many bits change on a
clock tick (lowest bit changes every time, bit#2 changes half
the time, bit #3 changes every fourth clock...) so there\'s
a log(N) scaling for N-bit counters\' average bit-change cost.
Capacitive energy loss thus favors a Gray code for counting
with minimal energy cost, (1) being the cost of each tick
incrementing the counter. There\'s some overhead, though,
because the determination of the \'next\' Gray code transition requires
a hidden internal logic behind the displayed bits.
What is the Gray counter scaling on transitions including the
hidden logic as well as the output bits?
whit3rd wrote:
In binary ripple counters, many bits change on a
clock tick...
Capacitive energy loss thus favors a Gray code for counting
with minimal energy cost, (1) being the cost of each tick
incrementing the counter. There\'s some overhead, though,
because the determination of the \'next\' Gray code transition requires
a hidden internal logic behind the displayed bits.
I did find this:
https://www.researchgate.net/post/really_Gray_consumes_lesser_power_than_binary_counter_is_it_true
On Wednesday, June 14, 2023 at 1:06:37?PM UTC-4, John Larkin wrote:
On Tue, 13 Jun 2023 13:04:09 -0700 (PDT), Ricky
gnuarm.del...@gmail.com> wrote:
On Tuesday, June 13, 2023 at 2:57:42?PM UTC-4, whit3rd wrote:
On Tuesday, June 13, 2023 at 12:26:34?PM UTC-4, Ricky wrote:
On Tuesday, June 13, 2023 at 11:57:55?AM UTC-4, whit3rd wrote:
Generating a one-Hz second hand drive would work OK from a 32727 Hz quartz
crystal with pseudorandom division, rather than the more common 32728 Hz value.
This is why I mentioned the issue of driving outputs, compared to strictly internal logic. If you are trying to design your own clock drive, I don\'t think you will do better on power than using a standard CMOS clock chip. In any event, the focus should be on the oscillator, rather than the divider.
Perhaps we have reached the X/Y point. You asked about X, but what is Y? What are you really trying to do?
I was advised that one high-end watch uses an electrostatic motor to drive the (sweep?) second
hand, but an electromagnetic (solenoid/ratchet?) drive for minutes. The claim was lower
energy use, allowing energy-harvesting to suffice.
I think it\'s this one:
https://www.digitaltrends.com/mobile/the-story-of-accutron-dna-world-first-twin-turbine-electrostatic-watch/
... and it got me thinking about the wasteful high-current-for-fast-slew clocking requirements of a flipflop.
32768 Hz is not \"fast\" in any sense. The energy used in digital logic is due to charging and discharging the capacitance of the circuit elements.
P = 1/2 C F V^2, where P is power, C is capacitance, F is frequency and V is voltage.
C F V^2. Both edges burn power.
You are confused. 1/2 C V^2 is the energy to charge a capacitor from a power source. Discharging a capacitor draws no power from the source. So only the charging at a rate of F is used in the equation of power. 1/2 C F V^2
On Friday, June 16, 2023 at 8:13:12â¯PM UTC-7, Les Cargill wrote:
whit3rd wrote:
In binary ripple counters, many bits change on a
clock tick...
Capacitive energy loss thus favors a Gray code for counting
with minimal energy cost, (1) being the cost of each tick
incrementing the counter. There\'s some overhead, though,
because the determination of the \'next\' Gray code transition requires
a hidden internal logic behind the displayed bits.
I did find this:
https://www.researchgate.net/post/really_Gray_consumes_lesser_power_than_binary_counter_is_it_true
Oh, that\'s exactly the answer; the shift-register type counters (pseudorandom sequences)
are clearly also worse than ripple counter, though their hardware implementation is attractively minimal.
I still think shift-register implementation of the phases necessary for a synchronous
secondhand drive (electrostatic motor) is the likely winner for a low-power
motor like that Accutron DNA product.
Continuing with the reverse-engineering thought experiment:
The minute-hand \'tick\' is the slowest clock required for that watch (with minutes/hours
being gear-connected). A crystal with power-of-two division to minutes(rather than seconds)
would be expected; nearest to the common 32768 Hz would be 30720 Hz.
Digikey doesn\'t stock that particular value, though: it\'d be a custom rock.
The minute-hand \'tick\' is the slowest clock required for that watch (with minutes/hours
being gear-connected). A crystal with power-of-two division to minutes(rather than seconds)
would be expected; nearest to the common 32768 Hz would be 30720 Hz.
Digikey doesn\'t stock that particular value, though: it\'d be a custom rock.
The lowest power divider will be a ripple counter where each stage is clocked by the output of the previous stage. You can\'t just compare the mode of the counters, you also need to compare the implementation.
The crystal frequency is not important. As you say, custom frequencies can be obtained. However, I\'m not sure of the cost. It seems frequencies around 32.768 kHz are very, very rare and I expect you need to buy a large number of units to lower the price of such a frequency.
On Saturday, June 17, 2023 at 11:26:09â¯AM UTC-7, Ricky wrote:
On Saturday, June 17, 2023 at 12:16:38â¯PM UTC-4, whit3rd wrote:
[about Accutron DNA watch]
The minute-hand \'tick\' is the slowest clock required for that watch (with minutes/hours
being gear-connected). A crystal with power-of-two division to minutes(rather than seconds)
would be expected; nearest to the common 32768 Hz would be 30720 Hz.
Digikey doesn\'t stock that particular value, though: it\'d be a custom rock.
The lowest power divider will be a ripple counter where each stage is clocked by the output of the previous stage. You can\'t just compare the mode of the counters, you also need to compare the implementation.
The crystal frequency is not important. As you say, custom frequencies can be obtained. However, I\'m not sure of the cost. It seems frequencies around 32.768 kHz are very, very rare and I expect you need to buy a large number of units to lower the price of such a frequency.
In the old days of AT-cut disks, that would be correct (off-spec units for TV colorburst made
it very inexpensive to get 4 MHz rocks). The tuning-fork crystals at 32 kHz, though,
are cut to rough frequency, then tuned by metal-plating the tines\' ends. It\'d be trivial to rescale,
and yields are high because the plating is an easy-to-adjust trim (adding thickness to a
ground-down quartz disk, is NOT easy).
On Saturday, June 17, 2023 at 11:26:09â¯AM UTC-7, Ricky wrote:
On Saturday, June 17, 2023 at 12:16:38â¯PM UTC-4, whit3rd wrote:
[about Accutron DNA watch]
The minute-hand \'tick\' is the slowest clock required for that watch (with minutes/hours
being gear-connected). A crystal with power-of-two division to minutes(rather than seconds)
would be expected; nearest to the common 32768 Hz would be 30720 Hz.
Digikey doesn\'t stock that particular value, though: it\'d be a custom rock.
The lowest power divider will be a ripple counter where each stage is clocked by the output of the previous stage. You can\'t just compare the mode of the counters, you also need to compare the implementation.
The crystal frequency is not important. As you say, custom frequencies can be obtained. However, I\'m not sure of the cost. It seems frequencies around 32.768 kHz are very, very rare and I expect you need to buy a large number of units to lower the price of such a frequency.
In the old days of AT-cut disks, that would be correct (off-spec units for TV colorburst made
it very inexpensive to get 4 MHz rocks). The tuning-fork crystals at 32 kHz, though,
are cut to rough frequency, then tuned by metal-plating the tines\' ends. It\'d be trivial to rescale,
and yields are high because the plating is an easy-to-adjust trim (adding thickness to a
ground-down quartz disk, is NOT easy).