Is 50 MHz doable for a complete newbie?

[Tobias Weingartner]

Hello all,

I'm a newbie when it comes to actually designing circuits at much
of anything above about 1MHz or so. And at that speed, you basically
just slap them together, and they basically work.

Now I'm looking at a circuit that will want to run at some 50MHz,
a CPU, FPGA, some SDRAM... I will be doing a PCB, but are there
other things I should be aware of? And good books/software, or even
practices to make this as painless as the 1MHz stuff was?

Any help, any pointers?


PS: I've read the "black magic" book, and I understand the ideas that
are presented within, but the actual application of most of those ideas
are completely beyond me at the current time.

--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Bob]

Tobias,

Clock rate will affect your setup and hold times.

Edge rate will affect the effect of reflections.

You got lucky, with modern IC's, if you just "threw everything together" at
1MHz and it worked.

Howard Johnson's (...Handbook of Black Magic) has its good points (and its
bad points), but as you've surmised, it doesn't teach you how to do
high-speed design. To me, it's more of a reference book.

Learn about:

* transmission line effects on signals
* data valid window on outputs
* data valid window on inputs (i.e., setup and hold time requirements of
each (and all) inputs)
* clock monotonicity requirements on inputs
* all of the various termination techniques
* logic family input and output characteristics (input/output levels, output
impedance, input impedance, edge rates, overshoot/undershoot
restrictions...)
* clocking distribution techniques (e.g., common low-skew distributed clocks
vs. clock forwarding)
* power supply bypassing techniques and requirements (especially bypass
capacitor parasitic effects)

After your grasp (really understand) these concepts, then you'll be ready to
start. Otherwise, you're just guessing.

Electromagnetics Explained, by Schmitt, is a very good book for some of
these concepts. The chapter on transmission lines is very good (although it
has a few typos).

Best of luck,
Bob


"Tobias Weingartner" <weingart@cs.ualberta.ca> wrote in message
news:slrnd1dje1.kf2.weingart@irricana.cs.ualberta.ca...

Hello all,

I'm a newbie when it comes to actually designing circuits at much
of anything above about 1MHz or so. And at that speed, you basically
just slap them together, and they basically work.

Now I'm looking at a circuit that will want to run at some 50MHz,
a CPU, FPGA, some SDRAM... I will be doing a PCB, but are there
other things I should be aware of? And good books/software, or even
practices to make this as painless as the 1MHz stuff was?

Any help, any pointers?


PS: I've read the "black magic" book, and I understand the ideas that
are presented within, but the actual application of most of those ideas
are completely beyond me at the current time.

--

[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[John Larkin]

On Sat, 19 Feb 2005 19:13:40 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:

In article <6rve111eqo2ou385oa50spkg4kof17ci2r@4ax.com>, John Larkin wrote:

50 MHz with conventional CMOS logic parts isn't bad. But spend a few
bucks more for a 4-layer (or more, if you need it) board with a solid
ground plane and a single or split power layer. After that, just keep
all the traces short (don't trust an autorouter! They tend to give
your most critical signals the Grand Tour of the board.)

I'll have to look into that. I'm not too well versed with anything
beyond 2 layers...

There are lots of ads in the backs of the electronics mags (EE Times,
ED, EDN) these days for cheap multilayer boards. What you're intending
sounds pretty much impossible to me on less than 4 layers, reasonable
on 6.

Sprinkle surface-mount bypass caps around, with vias to the ground
plane and the power plane/islands. Maybe four or so per chip per
supply voltage, and a few more here and there. Contrary to folklore,
you don't need one per power pin, nor do they have to be super-close
to the power pins. The best bypass cap is the capacitance between the
power and ground planes, so make that dielectric layer as thin as the
board house allows.

Hmm... so putting a cap onto each power/gnd pin on the cpu is not
100% necessary?

Not if you have decent power and ground layers. We just did a board
with a 32-bit uP, an XC2S600 BGA, and four 16 mbit fast srams; 4 caps
for the CPU, 4 for fpga core, 4 for fpga i/o, two per ram. Works great
at 55 MHz + 100 degrees C.

Plan your FPGA pinouts to minimize trace lengths and crossovers, and
contribute to the general beauty of the board.

Hoping to do that. But beauty without working won't help.

Beautiful layouts always work better!

Use series resistors (small surfmount arrays) in the lines to the
SDRAMS; try 33 ohms maybe, close to the CPU or FPGA driving the
memory.

Hmm... this I do not understand... guess I have to go see about
some existing circuit to see what they are doing. You mean think
of the data/address/control lines like a coax cable, and the 33 ohm
terms like the 50 ohm terminater I used to use when doing coax
ether?

Large arrays of drams are distributed capacitive loads and signals
tend to ring. The series Rs give you the option to trade off a little
speed for damping. But why the hassle of sdram? Unless you need a lot,
sram is a lot more friendly. You can get 1Mx16 superfast sram in a
package nowadays.

Which CPU and FPGA are you going to use? Bring out a few unused CPU
port pins and FPGA pins to test points.

I'm looking at an eZ80190 (VQFP-100) from Zilog, as well as an
XC3S400-4TQ144I from xilinx. Along with that, I'm hoping to put
together 8MB of flash, and 8MB of SDRAM. I'm thinking an XC9500XL
series should be able to handle at least the configuring of the
FPGA from the flash. (I'd like the flash to do double duty as flash
for the cpu as well as the fpga).

That should work. How will you load the uP code into the flash?

I'm not 100% sure if the XC9500XL would be good enough to handle
the logic for interfacing to the SDRAM for the CPU, and possibly
the FPGA as well (I know I can do it on the FPGA, but I'd rather
keep the FPGA "separate", something that another user can program
and not screw up the cpu completely).


My application needs the cpu, and the '400 FPGA from xilinx is big
enough and cheap enough for the other parts. I may be able to fit
my final verilog design into the '400 with it's own RAM blocks, but
I'd like to access the SDRAM for some of the parameters/"registers"/ram,
as that would reduce the pressure on the '400 significantly.

Basically, if the XC9500XL could arbitrate between the two (fpga/cpu),
and handle the sdram nastyness (timing, refresh/etc), and present
a SRAM type of interface to the FPGA/cpu, I think the rest could
be hacked together by me.


The FPGA needs to interface with the SDRAM (to read/write things).
All the unused pins will be brought out to other electronics, such
as ADCs, DACs, SCRs, etc, to interface with the outside world.

Sounds doable. But if this is your first shot at a thing like this,
budget for a second pass at the PCB layout, but try very hard to get
it right the first time.

John

 

[Larry Brasfield]

"Tobias Weingartner" <weingart@cs.ualberta.ca> wrote in message
news:slrnd1dje1.kf2.weingart@irricana.cs.ualberta.ca...

Hello all,
Hi, one.

I'm a newbie when it comes to actually designing circuits at much
of anything above about 1MHz or so. And at that speed, you basically
just slap them together, and they basically work.

Hmmm. That's not the way I remember the results
of such practises. You must lead a charmed life.

Now I'm looking at a circuit that will want to run at some 50MHz,
a CPU, FPGA, some SDRAM... I will be doing a PCB, but are there
other things I should be aware of?

Yes.

And good books/software, or even
practices to make this as painless as the 1MHz stuff was?

No.

Any help, any pointers?

This is not the right forum for a complete list of
gotcha's to avoid and tips to follow.

The most important thing to keep in mind as you go up in
frequency is that your idealizations of the circuit become
less and less accurate. Stray inductance and capacitance
create relatively larger effects, trace length become more
important due to reflections and radiation, and interference
effects (outbound and inbound) are more pronounced.

PS: I've read the "black magic" book, and I understand the ideas that
are presented within, but the actual application of most of those ideas
are completely beyond me at the current time.

I've never seen that book. The issues are well within
the realm of applied physics and mathematics. There
is no need for magic of any color or lack thereof.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

 

[John Larkin]

On Sat, 19 Feb 2005 05:25:21 +0000 (UTC), weingart@cs.ualberta.ca
(Tobias Weingartner) wrote:

Hello all,

I'm a newbie when it comes to actually designing circuits at much
of anything above about 1MHz or so. And at that speed, you basically
just slap them together, and they basically work.

Now I'm looking at a circuit that will want to run at some 50MHz,
a CPU, FPGA, some SDRAM... I will be doing a PCB, but are there
other things I should be aware of? And good books/software, or even
practices to make this as painless as the 1MHz stuff was?

Any help, any pointers?


PS: I've read the "black magic" book, and I understand the ideas that
are presented within, but the actual application of most of those ideas
are completely beyond me at the current time.

50 MHz with conventional CMOS logic parts isn't bad. But spend a few
bucks more for a 4-layer (or more, if you need it) board with a solid
ground plane and a single or split power layer. After that, just keep
all the traces short (don't trust an autorouter! They tend to give
your most critical signals the Grand Tour of the board.)

Sprinkle surface-mount bypass caps around, with vias to the ground
plane and the power plane/islands. Maybe four or so per chip per
supply voltage, and a few more here and there. Contrary to folklore,
you don't need one per power pin, nor do they have to be super-close
to the power pins. The best bypass cap is the capacitance between the
power and ground planes, so make that dielectric layer as thin as the
board house allows.

Plan your FPGA pinouts to minimize trace lengths and crossovers, and
contribute to the general beauty of the board.

Use series resistors (small surfmount arrays) in the lines to the
SDRAMS; try 33 ohms maybe, close to the CPU or FPGA driving the
memory.

Put test points (just pads with thru-holes big enough for a scope
probe tip to park in) on everything interesting: powers, clocks, chip
selects, ras/cas type things, one CPU port pin for timing subroutines.
No matter how many you put, you'll regret not having more. At speed, a
scope probe needs a good ground, so add a bunch of small (4-40 or
2-56) sized holes, grounded, and put in screws, pointing up, as places
to clip probe grounds.

Don't forget board mounting holes. Grounded, of course.

LEDs are always fun. We use SOT-23 led's to indicate successful FPGA
configuration, CPU heartbeat, power-on, stuff like that.

Which CPU and FPGA are you going to use? Bring out a few unused CPU
port pins and FPGA pins to test points.

John

 

[Tobias Weingartner]

In article <6rve111eqo2ou385oa50spkg4kof17ci2r@4ax.com>, John Larkin wrote:

50 MHz with conventional CMOS logic parts isn't bad. But spend a few
bucks more for a 4-layer (or more, if you need it) board with a solid
ground plane and a single or split power layer. After that, just keep
all the traces short (don't trust an autorouter! They tend to give
your most critical signals the Grand Tour of the board.)

I'll have to look into that. I'm not too well versed with anything
beyond 2 layers...

Sprinkle surface-mount bypass caps around, with vias to the ground
plane and the power plane/islands. Maybe four or so per chip per
supply voltage, and a few more here and there. Contrary to folklore,
you don't need one per power pin, nor do they have to be super-close
to the power pins. The best bypass cap is the capacitance between the
power and ground planes, so make that dielectric layer as thin as the
board house allows.

Hmm... so putting a cap onto each power/gnd pin on the cpu is not
100% necessary?

Plan your FPGA pinouts to minimize trace lengths and crossovers, and
contribute to the general beauty of the board.

Hoping to do that. But beauty without working won't help.

Use series resistors (small surfmount arrays) in the lines to the
SDRAMS; try 33 ohms maybe, close to the CPU or FPGA driving the
memory.

Hmm... this I do not understand... guess I have to go see about
some existing circuit to see what they are doing. You mean think
of the data/address/control lines like a coax cable, and the 33 ohm
terms like the 50 ohm terminater I used to use when doing coax
ether?

Which CPU and FPGA are you going to use? Bring out a few unused CPU
port pins and FPGA pins to test points.

I'm looking at an eZ80190 (VQFP-100) from Zilog, as well as an
XC3S400-4TQ144I from xilinx. Along with that, I'm hoping to put
together 8MB of flash, and 8MB of SDRAM. I'm thinking an XC9500XL
series should be able to handle at least the configuring of the
FPGA from the flash. (I'd like the flash to do double duty as flash
for the cpu as well as the fpga).

I'm not 100% sure if the XC9500XL would be good enough to handle
the logic for interfacing to the SDRAM for the CPU, and possibly
the FPGA as well (I know I can do it on the FPGA, but I'd rather
keep the FPGA "separate", something that another user can program
and not screw up the cpu completely).


My application needs the cpu, and the '400 FPGA from xilinx is big
enough and cheap enough for the other parts. I may be able to fit
my final verilog design into the '400 with it's own RAM blocks, but
I'd like to access the SDRAM for some of the parameters/"registers"/ram,
as that would reduce the pressure on the '400 significantly.

Basically, if the XC9500XL could arbitrate between the two (fpga/cpu),
and handle the sdram nastyness (timing, refresh/etc), and present
a SRAM type of interface to the FPGA/cpu, I think the rest could
be hacked together by me.


The FPGA needs to interface with the SDRAM (to read/write things).
All the unused pins will be brought out to other electronics, such
as ADCs, DACs, SCRs, etc, to interface with the outside world.

--
*----------------------------------------------------------------------------*
| Tobias Weingartner | Unix Guru, Admin, Systems-Dude, ... |
| Apt B 7707-110 St. |-----------------------------------------------------|
| Edmonton, AB T6G 1G3 | %SYSTEM-F-ANARCHISM, The OS has been overthrown |
*----------------------------------------------------------------------------*
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

 

[Tobias Weingartner]

In article <e7cf11d9amsilfb949g4sr70igauusmm5q@4ax.com>, John Larkin wrote:

There are lots of ads in the backs of the electronics mags (EE Times,
ED, EDN) these days for cheap multilayer boards. What you're intending
sounds pretty much impossible to me on less than 4 layers, reasonable
on 6.

Oh, getting 4-6 layer boards done ain't that hard... I can get them
done through the university, or even expresspcb/etc. I guess I'm going
to shoot for 4, and not be surprised if I hit 6.

Not if you have decent power and ground layers. We just did a board
with a 32-bit uP, an XC2S600 BGA, and four 16 mbit fast srams; 4 caps
for the CPU, 4 for fpga core, 4 for fpga i/o, two per ram. Works great
at 55 MHz + 100 degrees C.

I'd love to know more if possible. I'm always looking for examples
that I can look at, and imitate.

Plan your FPGA pinouts to minimize trace lengths and crossovers, and
contribute to the general beauty of the board.

Hoping to do that. But beauty without working won't help.

Beautiful layouts always work better!

Good to know. Beauty is what I'll go for.

Use series resistors (small surfmount arrays) in the lines to the
SDRAMS; try 33 ohms maybe, close to the CPU or FPGA driving the
memory.

Hmm... this I do not understand... guess I have to go see about
some existing circuit to see what they are doing. You mean think
of the data/address/control lines like a coax cable, and the 33 ohm
terms like the 50 ohm terminater I used to use when doing coax
ether?

Large arrays of drams are distributed capacitive loads and signals
tend to ring. The series Rs give you the option to trade off a little
speed for damping. But why the hassle of sdram? Unless you need a lot,
sram is a lot more friendly. You can get 1Mx16 superfast sram in a
package nowadays.

At that point, I'd be looking at putting 4 of those on the board. I
suppose that's not too much. Along with some logic to address them
in a byte wise fashion.

Which CPU and FPGA are you going to use? Bring out a few unused CPU
port pins and FPGA pins to test points.

I'm looking at an eZ80190 (VQFP-100) from Zilog, as well as an
XC3S400-4TQ144I from xilinx. Along with that, I'm hoping to put
together 8MB of flash, and 8MB of SDRAM. I'm thinking an XC9500XL
series should be able to handle at least the configuring of the
FPGA from the flash. (I'd like the flash to do double duty as flash
for the cpu as well as the fpga).

That should work. How will you load the uP code into the flash?

Ideally I'd like the cpu to do it (more logic) with a monitor type
of program. Serial download of new firmware. But until I get to
that point, jtag will likely have to be it.

Sounds doable. But if this is your first shot at a thing like this,
budget for a second pass at the PCB layout, but try very hard to get
it right the first time.

I think I'll be budgeting for 3 in the end.

--
*----------------------------------------------------------------------------*
| Tobias Weingartner | Unix Guru, Admin, Systems-Dude, ... |
| Apt B 7707-110 St. |-----------------------------------------------------|
| Edmonton, AB T6G 1G3 | %SYSTEM-F-ANARCHISM, The OS has been overthrown |
*----------------------------------------------------------------------------*
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax