Infer DDR registers from RTL?

[Anil Khanna]

Hi all,

Does anyone know the right steps to make ISE infer DDR registers from a RTL
code? I am following the template that ISE suggests in their answer record
#15776. Apart from this, I also make sure to set the IOB option during MAP.
I still cannot see the dual-data rate flops being used in the map report.

However, when I open FPGA editor, I can see that my two flops were mapped to
registers that are placed in the same IOB. How do I know for a fact that the
IFDDRSE (or a corresponding) primitive is actually being used?

Thanks

Anil

 

[praveen]

anil,
can i know which is your target device.
as per my knowledge dual edge triggered flip flop is supported only in
Cool Runner - II.

"Anil Khanna" <anil_khanna@mentor.com> wrote in message news:<3fa97de8$1@solnews.wv.mentorg.com>...

Hi all,

Does anyone know the right steps to make ISE infer DDR registers from a RTL
code? I am following the template that ISE suggests in their answer record
#15776. Apart from this, I also make sure to set the IOB option during MAP.
I still cannot see the dual-data rate flops being used in the map report.

However, when I open FPGA editor, I can see that my two flops were mapped to
registers that are placed in the same IOB. How do I know for a fact that the
IFDDRSE (or a corresponding) primitive is actually being used?

Thanks

Anil