inequality with std_logic_vector in what package is defined

Hi,
I wonder in what packages the inequality like <, <= involving std_logic_vector operators are defined. I wrote the code below, compiled it with modelsim and it worked fine. However std_logic_1164 package does not have the defintion of < with std_logic_vector..so how the result is computed?
Cheers



library ieee;
use ieee.std_logic_1164.all;

entity comp is
port (a,b: in std_logic_vector(3 downto 0);
ctrut std_logic);
end entity;

architecture behaviour of comp is
begin
ctr<='1' when (a<b) else
'0';
end;

 

[Alan Fitch]

On 29/11/13 20:20, thierrybingo@googlemail.com wrote:

Hi,
I wonder in what packages the inequality like <, <= involving std_logic_vector operators are defined. I wrote the code below, compiled it with modelsim and it worked fine. However std_logic_1164 package does not have the defintion of < with std_logic_vector..so how the result is computed?
Cheers



library ieee;
use ieee.std_logic_1164.all;

entity comp is
port (a,b: in std_logic_vector(3 downto 0);
ctrut std_logic);
end entity;

architecture behaviour of comp is
begin
ctr<='1' when (a<b) else
'0';
end;

It's part of the language - any enumerated type has implicit operators
(<, > etc) based on the position of the literals in the type. In
std_logic, '1' is to the left of '0', so '1' is considered greater than '0'.

So if
a) the vectors are the same length and
b) you are thinking of them as "unsigned"
c) you don't try and compare e.g. 'H' and '0'

it works. However if you are thinking of your vectors as representing
signed numbers, or they are of different lengths, or they contain values
that are not '0' or '1', strange (but well-defined) things will happen,

regards
Alan

--
Alan Fitch

 

[Jim Lewis]

Anytime you are doing math on vectors, you should use a math type (such as unsigned, signed, ufixed, sfixed, float, integer). For unsigned and signed I recommend using the IEEE standard package "ieee.numeric_std.all" (rather than the shareware package "ieee.std_logic_arith.all").

If this is the only math usage of a and b, you can do:
ctr<='1' when (unsigned(a) < unsigned(b)) else '0';

If you tool supports VHDL-2008, you can get an unsigned interpretation of std_logic_vector by using "ieee.numeric_std_unsigned.all". However, over the life of a project, using a math type is a better from a documentation stand point.

If your synthesis tool does not support VHDL-2008, you can use the shareware package, "ieee.std_logic_unsigned.all" to accomplish the same thing.

If you use a relational and the vectors are not the same length or they contain an H or L, then the results will not match the desired numeric results.. IE: "100" > "01001" will return true. So I recommend using package "numeric_std_unsigned" to protect against this.

Jim