Index Array (Yet Another Question)

[Filipa]

Hi,

I found several questions posted about array indexing but I am still
confused on how can I solve my problem.
I have a memory array that I want to index with a hot-one address.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity memory is
generic( addr_width : integer := 5;
data_width : integer := 4);
port(
Q : out std_logic_vector(data_width - 1 downto 0 );
R_ADR : in std_logic_vector(2**addr_width - 1 downto 0);
W_ADR : in std_logic_vector(2**addr_width - 1 downto 0);
D : in std_logic_vector(data_width - 1 downto 0 );
W : in std_logic;
R : in std_logic;
ME : in std_logic;
CLK : in std_logic
);
end memory;


architecture synth_mem of memory is
type mem_array is array (std_ulogic range <&gt of std_logic_vector
(data_width - 1 downto 0 );
signal ram : mem_array(2**addr_width - 1 downto 0);

-- function hot_to_int(hot: std_logic_vector(2**addr_width - 1
downto 0)) return integer is
-- variable conv : integer := 0;
-- begin
-- for i in 0 to 2**addr_width - 1 loop
-- if hot(i) = '1' then
-- conv := i;
-- end if;
-- end loop;
-- return conv;
-- end hot_to_int;

begin
-- process (ME, CLK)
-- begin
-- if ME = '1' then
-- Q <= (others => '1');
-- elsif CLK'event and CLK = '1' then
-- if R = '1' then
-- Q <= ram(R_ADR);
-- else
-- Q <= (others => '1');
-- end if;
---- if W = '1' then
---- ram(W_ADR) <= D;
---- end if;
-- end if;
-- end process;

ram(W_ADR) <= D when (W = '1' and CLK = '0');
Q <= ram(R_ADR) when (R = '1' and CLK = '0');

end synth_mem;

 

[Jim Lewis]

Filipa,
add package:
use ieee.numeric_std.all ;

Some may tell you to remove the following package.
It is not necessary to do this, but since it is not
used here, there is no reason to include it either.
use ieee.std_logic_unsigned.all;


Array indicies must be based on a discrete type and are
commonly based on integer or one of its subtypes.
While std_ulogic is a discrete type, it only gives you
9 index values and it most certainly does not take std_logic_vector
as an index

type mem_array is array (std_ulogic range <&gt of std_logic_vector
(data_width - 1 downto 0 );

So change your type declaration to:
type mem_array is array (natural range <&gt of
std_logic_vector(data_width - 1 downto 0 );
signal ram : mem_array(2**addr_width - 1 downto 0);

Now use a conversion when writing to RAM:
ram(to_integer(unsigned(W_ADR)) <= ...
. . .
And likewise when you are reading the RAM:
Q <= ram(to_integer(unsigned(R_ADR)) ...

Now make the rest of your logic reflect the device
you are trying to model (perhaps at one time it was).

Cheers,
Jim

Hi,

I found several questions posted about array indexing but I am still
confused on how can I solve my problem.
I have a memory array that I want to index with a hot-one address.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity memory is
generic( addr_width : integer := 5;
data_width : integer := 4);
port(
Q : out std_logic_vector(data_width - 1 downto 0 );
R_ADR : in std_logic_vector(2**addr_width - 1 downto 0);
W_ADR : in std_logic_vector(2**addr_width - 1 downto 0);
D : in std_logic_vector(data_width - 1 downto 0 );
W : in std_logic;
R : in std_logic;
ME : in std_logic;
CLK : in std_logic
);
end memory;


architecture synth_mem of memory is
type mem_array is array (std_ulogic range <&gt of std_logic_vector
(data_width - 1 downto 0 );
signal ram : mem_array(2**addr_width - 1 downto 0);

-- function hot_to_int(hot: std_logic_vector(2**addr_width - 1
downto 0)) return integer is
-- variable conv : integer := 0;
-- begin
-- for i in 0 to 2**addr_width - 1 loop
-- if hot(i) = '1' then
-- conv := i;
-- end if;
-- end loop;
-- return conv;
-- end hot_to_int;

begin
-- process (ME, CLK)
-- begin
-- if ME = '1' then
-- Q <= (others => '1');
-- elsif CLK'event and CLK = '1' then
-- if R = '1' then
-- Q <= ram(R_ADR);
-- else
-- Q <= (others => '1');
-- end if;
---- if W = '1' then
---- ram(W_ADR) <= D;
---- end if;
-- end if;
-- end process;

ram(W_ADR) <= D when (W = '1' and CLK = '0');
Q <= ram(R_ADR) when (R = '1' and CLK = '0');

end synth_mem;

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis SynthWorks VHDL Training http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.