I hate VHDL!!!

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[Just an Illusion]

Hi Weng,

A little question for you,

If you have this code :

if (C1) then
...
elsif (C2) then
...
endif

and if you know that C1 and C2 are mutually exclusive, why don't simply
write ? ;-)

if (C1) then
...
endif

if (C2) then
...
endif

If you reply me by 'if...then...elsif...then...else...endif', I give you
immediatly the solution:

process (...)
variable temp : type;
begin
temp := elsevalue;
if (C1) then
temp := C1value;
end if;
if (C2) then
temp := C2value;
end if;
...
S <= temp;
end process;

That give you the expected result, and you have no more relation between
C1 and C2.

I am agree, you continue to check the value of C1, but I am not sure
that you 'loose' the same among of time that with the 'elsif' structure.
Somewhere this method is equivalent to a case structure, if C1 and C2
have the same 'bit length' structure (i.e. can be express as a bus, and
give one value by condition).

That doesn't invalidate your idea, but you can seen that VHDL have the
possibility to implement this structure, and can give some information
on uncorrelation between signals (for compiler).
I seen one advantage with you notation; during the VHDL origin, people
want make a 'language' with more abstraction (than transistor and
logical gate). Your proposal continue this concept.

JaI

Weng Tianxiang wrote:

1. I deeply believe that sooner or later the key words
"orif"/"orels"/"errels" will be introduced into VHDL.
2. I think the task is laid on Jim Lewis shoulder, he is my paper
reviewer, "errels" suggestor and member of VHDL committee. Now he is
fully qualified to do that. I will help him push the movements.
3.
"The "orif"/"orels"/"errels" keywords are an interesting concept"
I am glad that your attitude changes from "brainless troll" to
"interesting concept".

It is just a tip of iceberg. Its power is far more than what you have
thought.
For example, all 5 methods(yours, my 2, engineer from IBM and Lockheed
Martin) fail when states of state machine are declared in enumerated
type(I never declare states as coded numbers to save time and energy
to elsewhere).
In general, the key words "orif"/"orels"/"errels" provide VHDL users
with very powerful tools to deliver any useful mutually exclusive
information well known to designers to VHDL compilers and it will
"immediately" reduce resource waste and increase final project speed
without big code change(change from "elsif" to "orif" delivers the
information to compiler) .

The following is an example:

If(A1) then // maybe if(A1 or A2 or A3) then
NextState <= state1;
orIf(A2) then // A1 will be excluded in final equation here
NextState <= state2;
orIf(A3) then // A1/A2 will be excluded in final equation here
NextState <= state3;
elsIf(A4) then // maybe elsif(A4 or A5 or A6) then
NextState <= state4;
orif(A5) then // A4 will be excluded in final equation here
NextState <= state5;
orIf(A6) then // A4/A5 will be excluded in final equation here
NextState <= state6;
elsIf(A7) then
NextState <= state7;
orIf(A8) then // A7 will be excluded in final equation here
NextState <= state8;
else
NextState <= state0;
end if;

It tell compilers that there are 3 groups of conditions that are
mutually exclusive:
A1/A2/A3;
A4/A5/A6;
A7/A8;

Further more logic saving can be achieved if you select common factor.
For example:
A1 <= B1 and C1;
A2 <= B1 and C2;
A3 <= B1 and C3;
"if(A1 or A2 or A3) then"
can be replaced by
"if(B1) then"

or
If(A1) then // maybe if(A1 or A2 or A3) then
Data <= Data1;
orif(A2) then // A1 will be excluded in final equation here
Data <= Data2;
orif(A3) then // A1/A2 will be excluded in final equation here
Data <= Data3;
elsif(A4) then // maybe elsif(A4 or A5 or A6) then
Data <= Data4;
orif(A5) then // A4 will be excluded in final equation here
Data <= Data5;
orif(A6) then // A4/A5 will be excluded in final equation here
Data <= Data6;
elsIf(A7) then
Data <= Data7;
orIf(A8) then // A7 will be excluded in final equation here
Data <= Data8;
else
Data <= Data0;
end if;

In another words, the power of 3 keywords is that
with any declaration to compiler that there are mutually exclusive
conditions, you get benefits in both speed and resources!!!

As we know, the most effective expression in VHDL is case statement.
The more case statement you use, the more efficient your design is.
Why? It indicates to compiler that there are mutually exclusive
relations. Case statement has a drawback: the case variable must be a
state machine name or it must have fixed number of bits. Again, why?
The reason is in a state machine, all states are mutually exclusive.
For a fixed number of bits, all different values are mutually
exclusive.
OK, now I would like to tell in real world there are far more
situations where there are mutually exclusive situations than 2 above
cases: not only within one state machine there are mutually exclusive
relations, there are possibilities that mutually exclusive relations
exist among a group of state machines if you can recognize them. In my
paper, I enumerated 11 cases where mutually exclusive relation may
exist. 3 years later I have accumulated more than that.

For example, let us refer to PCI transactions. If a PCI write
transaction is targeting at one of 4 spaces of a device, the 4 write
state machines in 4 different spaces are mutually exclusive: Only one
working state is permitted at any time among the 4 state machines.
This is why I suggest another two key words "machine" and "exclusive"
to declare which state machine is mutually exclusive with others.

Now VHDL standard become bottleneck, the code inefficiency source.
Why? it fails to provide users with a means to declare non-standard
mutually exclusive conditions that are ubiquitous.

 

[Mike Treseler]

Chao wrote:

At first thanks for Mike's answer. But my exact question was how to
extract so many many internal signals which are listed during the
timing simulation. For example, _inbuf, _ibuf, _gst, etc. How can I
know which signal represents my original input signal or output
signal?

The job of synthesis is to create a netlist of primitives
(like dffe, inbuf etc. ) that sims the same as your code.
You can view the netlist on tools like leonardo.
I don't know of any way to relate primitives to your
source code.

Normally synthesis "just works".
When it doesn't consider the following.

1. Double check the static timing report and synthesis warnings.
2. Eliminate asynchronous processes and multiple clocks.
3. Double check all inputs for synchronization.
4. Break the design into pieces zoom in on the problem.

Good luck,

-- Mike Treseler

 

[roller]

"Weng Tianxiang" <wtx@umem.com> escribió en el mensaje
news:511e4538.0406140750.b16a530@posting.google.com...

'if..elsif..elseif..endif' generates following equation:
A1.B1 + !A1.A2.B2 + !A1.!A2.A3.B3

If A1, A2 and A3 are mutually exclusive, and my suggestion is used:
'if..ORIF..ORIF..endif'
you will get the equation:
A1.B1 + A2.B2 + A3.B3
Same equation as if a "case" statement were used.

1. You tell compiler to generate statements like "case" statement.

so, again you admit that it'd be the same than a case statement....as you
previously admitted that there was no logic change while another poster
showed that indeed there was a possible optimization (something like the
solution i gave in the first place)

2. More items means long route, longer delay and decreased running
frequency.

The speed-up and resource saving is the FPGA chip final result, not
simulation!
I have never mentioned simulation saving.

When you don't fully understand a situation, you may feel it
"dangerous", "can of worm", "Pandora's box". But when you understand
it, it will makes your chip run faster and with confidence and without
any new simulation burden if and only if VHDL provides a means to do
that!

A CONCLUSION OF MUTUALLY EXCLUSIVE CONDITIONS IS NOT BASED ON THEIR
CONDITION VALUES, BUT ON PHYSICAL CONDITIONS!!!

no need to shout...

You are sleeping, you cannot be eating. And you are eating, you cannot
be sleeping;
You are at home, you cannot be at theater, you are at theater, you
cannot be at home;
You are dead, you cannot be alive, you are alive, you cannot be dead;
You are 20 years old, you cannot be 40 years old, you are 40 years
old, you cannot be 20 years old;
A true $20 note cannot be false, a false $20 note cannot be true;

But "You are a son, you cannot be a father, you are a father, you
cannot be a son" is wrong!!! You don't have to do simulations, no, not
a second, to prove if they are mutually exclusive.

So there is no confusion at all and there is never a "rare" "critical"
boundary condition to be tested!!!

If you can provide me with an example, I will tell you where you are
wrong.

no need, you didnt answer any of my previous questions on the
first place. And besides, i'll say it again, you ended up admitting that
your new keywords are identical to a "case", and also that there was no
logic
change.
In anycase, I agree with Tom (wallclimber)

> Weng

 

[Ray Andraka]

Yes, but not with the approach you are currently using. You have 80 DSP
blocks. The multipliers in those are capable of quite a bit more than 80
MHz. One possibility is to time multiplex the data into the same filter,
running it at 4x the clock rate. Now 320 MHz is not an easy target,
especially for a new user. If you are also mixing to baseband, you could
use a polyphase decimator architecture to reduce the sample rate seen at
each multiplier. Another option, is to use distributed arithmetic, which
is a technique whereby the multiplications are rearranged at the bit level
to take advantage of the small luts in the FPGA fabric. It won't use the
DSP blocks in that case. As with many things, there is more than one way
to approach the problem.

Patrick wrote:

hello,

I'm working about a DQPSK modem 4 Mbits/s.

My problem is to implant the 4 nyquist filter (on (I and Q) *2
(transmitter and receiver).

I use a Stratix - FPGA.

When I developp the filter with ONLY 12 taps the four filters utilizes
76 DSP block and I have only 80 DSP blocks.

After Matlab simulation, I must have 48 taps for a correct impulse
response.

The sampling frequency is 80 MHz and the filter bandpass is 2 MHz.

Is it possible to implant 4 filters with 48 taps in a single Stratix
FPGA.

thanks for response

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Egbert Molenkamp]

I assume the initialization file is a text file.
Have a look at (and following chapters)
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#files

I added a corrected version (see --**)

architecture behavioral of ShiftReg is
subtype word is std_logic_vector(15 downto 0);
begin
P: process (clk, shift, ld,reset)
file datain : TEXT open read_mode is
"C:/Modeltech_xe_starter/examples/ch 10/init.txt";
variable d : bit_vector(15 DOWNTO 0); --**
variable L : line; --**
begin
if (reset='1') then
while not(endfile(datain)) loop
readline(datain,L); --**
read(L,d); --**
q <= to_stdlogicvector(d); --**
end loop;
elsif ( clk'event and clk ='1') then
if (shift = '0') and (ld='1') then
q <= d_in ;
elsif (shift = '1') then
q(14 downto 0) <= q(15 downto 1) ;
q(15) <= serial_in ;
-- alternative for previous two lines is: q <= serial_in & q (15
downto 1);
end if;
end if;
end process P;
end architecture behavioral;

Egbert Molenkamp

"SR" <gtg418c@mail.gatech.edu> wrote in message
news:calu86$ss2$1@news-int2.gatech.edu...

Hello,

I am trying to simulate a 16-bit shift register using the following
program:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use std.textio.all;

entity ShiftReg is
Port (d_in : in std_logic_vector(15 downto 0);
serial_in,ld,shift,clk,reset : in std_logic;
q : inout std_logic_vector(15 downto 0));
end entity ShiftReg;

architecture behavioral of ShiftReg is
subtype word is std_logic_vector(15 downto 0);
type initz is file of word;
begin
P: process (clk, shift, ld,reset)
file datain : initz open read_mode is
"C:/Modeltech_xe_starter/examples/ch 10/init.txt";
variable val : word;

begin
if (reset='1') then
while not(endfile(datain)) loop
read(datain,val);
end loop;
elsif ( clk'event and clk ='1') then
if (shift = '0') and (ld='1') then
q <= d_in ;
elsif (shift = '1') then
q(14 downto 0) <= q(15 downto 1) ;
q(15) <= serial_in ;
end if;
end if;
end process P;
end architecture behavioral;

The file init.txt just contains the string 1110000000000001

And the simulation settings that I used where

force clk '0' 1 ns, '1' 2 ns -repeat 2 ns
force reset '1','0' 3 ns
force ld '0'
force d_in '0000111100001111'
force shift '0'
force serial_in '0'

What happens is that the variable val remains undefined and as a result
q always remains undefined.If someone can help me with as to why this
program does not read in from the file, I would be much obliged.

Thanks, and I appreciate the consideration.

Mani

 

[Just an Illusion]

Hi Naveed,

The only way ;-( that I know to ensure it, it's generate a hardware
reset just after, or during, power up. Some different techniques work,
for bigger circuit, then it must be possible todo it with a cpld too ;-)

You can play with 'pull-up' transistor directly on spice netlist, but I
am not sure that CPLD take it into account.

Have a fun ;-)
JaI

MNQ wrote:

Hello JaI

Not for use in a simulator but for real life running of CPLD.

Thanks for replying

Naveed

"Just an Illusion" <illusion_to_net@yahoo.fr> wrote in message
news:40D192C1.5000306@yahoo.fr...


In simulator ?
Write a testbench which instantiate your component, and do a reset
(reset=1) at start.

JaI

MNQ wrote:



Hi All,

I am trying to find out how I can set my initial value of BUSY in the
process below to '1' i.e. at T=0 for when power is first applied to my
device (CPLD XC2C384).

My process is as follows:-

busy_FF : process (busy_clock, reset, buf_busy)
begin
if reset ='1' then
busy <= '1';
elsif busy_clock='1' and busy_clock'event then
busy <= not buf_busy;
end if;
end process busy_FF;


Thanks for any help

Naveed

 

[Tim Hubberstey]

MNQ wrote:

Hi All,

I am trying to find out how I can set my initial value of BUSY in the
process below to '1' i.e. at T=0 for when power is first applied to my
device (CPLD XC2C384).

My process is as follows:-

busy_FF : process (busy_clock, reset, buf_busy)
begin
if reset ='1' then
busy <= '1';
elsif busy_clock='1' and busy_clock'event then
busy <= not buf_busy;
end if;
end process busy_FF;

The normal way would be through application of the reset signal --
that's what it's for.

Coolrunner devices go through an initialization phase at power-up where
they copy their flash contents to internal RAM cells. I would expect
that you should be able to specify, somehow, what you want the register
values to be following initialization (I don't know this for sure). I
took a quick look at this and the answer isn't readily obvious so this
is a question for Xilinx, or you might try in comp.arch.fpga.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Chaos Master]

Tom Hawkins (tom1@launchbird.com) said those last words:

Do you want to learn VHDL, or do you want to learn HDL-based hardware
design? If the later, I would recommend Confluence. As a functional
programming language, Confluence designs typically result in 3-5X
fewer lines of code than VHDL. The CF compiler returns HDL and a
cycle accuarte C model -- compile with GCC and you've got yourself a
high-performance logic simulator.

I will take a look on those all suggestions. Many thanks!
--
Š Chaos Master. |"These wounds won't seem to heal
My Evanescence HP is at: | This pain is just too real
http://marreka.no-ip.com | There's just too much that time can't erase"
(most often offline... ) | -- Evanescence, "My Immortal"

 

[Ken Smith]

In article <carh6s$vdm@newton.cc.rl.ac.uk>,
Matt North <m.r.w.north@NO_SPAMrl.ac.uk> wrote:

I have a nice one that is about a 25 pounder. Its XP compatible.

Sounds good........i'm seriously thinking of upgrading to a THOR AP12
Aluminium and plastic hammer.
It gives the user a choice of persuasive use with the plastic head or
destruction with the aluminium head.

Now that THOR inc. has been bought out by McDisneyMart Corp. they import
cheap junk and put their label on it. If the head isn't hand forged it
won't completely uninstall XP from the hard disk.

--
--
kensmith@rahul.net forging knowledge

 

[Egbert Molenkamp]

The design entity in your file not_imp.vhd is simulated correctly but I have
the feeling that the port declaration in entity declaration of not_imp is
not EXACTLY the same is the port declaration in the component declaration.
Copy and paste the port declaration.

Egbert Molenkamp

"Luca" <ifuicnap@lombardiacom.it> wrote in message
news:aoi3d05l7v1un15fibobjs8kfdff2tc114@4ax.com...

Hello! I have a problem to solve with Modelsim XE II and I'd be very
happy if you helped me. When I compile a vhdl file for a latch-D, I
get a success message; but whet I launch it for a simulation, I always
get the following message:
"Warning: (vsim-3473) Component 'not0' is not bound."

This is the file latch_D.vhd:

entity latch_D is
port(D,Ck:in bit;
Q,Qbarut bit);
end latch_D;
architecture latch_D_arc of latch_D is
component latch_SR
port(S,R,Ck: in bit;
Q,Qbar: out bit);
end component;
component NOT_IMP
port(A: in bit;
Abarut bit);
end component;
signal Dbar : bit;
begin
not0: NOT_IMP
port map (D,Dbar);
latch_SR0: latch_SR
port map (D,Dbar,Ck,Q,Qbar);
end latch_D_arc;

Both not_imp.vhd and latch_SR.vhd give success in compiling and work
great in simulation, but the latch_D doesn't work. Can you help me?
Thanks!!

 

[Just an Illusion]

Hi,

Are you sure that you have compile 'not_imp' architecture in the same
working library that 'latch_d' ?

Compilation doesn't definitively check presence of compiled architecture.
During compilation, tools check only that all component interface (or
prototype) is well defined (via package usage from library or in
architecture_declarative_part).

During the phase of instantiation, the tools try to bound them, and that
is the possible source of the warning (if the component isn't compile in
same working library, or library add through library_clause and use_clause).

Be happy ;-)
JaI

Luca wrote:

Hello! I have a problem to solve with Modelsim XE II and I'd be very
happy if you helped me. When I compile a vhdl file for a latch-D, I
get a success message; but whet I launch it for a simulation, I always
get the following message:
"Warning: (vsim-3473) Component 'not0' is not bound."

This is the file latch_D.vhd:

entity latch_D is
port(D,Ck:in bit;
Q,Qbarut bit);
end latch_D;
architecture latch_D_arc of latch_D is
component latch_SR
port(S,R,Ck: in bit;
Q,Qbar: out bit);
end component;
component NOT_IMP
port(A: in bit;
Abarut bit);
end component;
signal Dbar : bit;
begin
not0: NOT_IMP
port map (D,Dbar);
latch_SR0: latch_SR
port map (D,Dbar,Ck,Q,Qbar);
end latch_D_arc;

Both not_imp.vhd and latch_SR.vhd give success in compiling and work
great in simulation, but the latch_D doesn't work. Can you help me?
Thanks!!

 

[Just an Illusion]

Hi Weng,

Weng Tianxiang wrote:

...

"if..elsif..elsif..endif" structure is Fortran language's product. In
software, there is no impact on performance, everything must be
executed in serial order.

Do you know that the vhdl origin is ada, not fortran

But in hardware, its essence is concurrent implementation.

I am not agree with you about this point, 'case' is the concurrent

implementation 'spirit'; 'if' defined a policy of priority then you
expected than you found a mux cascade at the end.

"if..orif..orif..endif" structure provides a similar, but excellent
structure to supplement "if..elsif..elsif..endif" structure: either in
serial implementation area or in concurrent implementation area.


An other remark, you haven't any 'serial' implementation area, but

'sequential' ;-)

And neither 'if' nor 'case' can be define into a concurrent statement
area. They are typically sequential statement (must be embedded into a
process statement part, that is a sequential statement). It is not
because process executions are concurrent, than there 'code' is
concurrent too.

Weng


Rgrds,

JaI

 

[Just an Illusion]

Hi Jluis,

First, please don't shout.

Second see the thread on Free HDL simulator for simulation.

For synthesis, I don't know real 'free' synthesizer (free and without
any limit of time, complexity, target fpga...)

You can try Leonardo Spectrum, but if you have a dedicated fpga, you can
find some 'free' tool suite given by Altera (for Altera fpga), Xilinx
(for them), etc.

Rgrds,
JaI

Jluis wrote:

Hi!!!

actually I´m looking for all the tools to simulate and synthesis
programs in VHDL. by the way I saw a vhdl generator from C CODE FROM
CELOXICA. BUT IT´S Not FREEWARE. hehehe.

COULD ANYBODY SEND ME LINKS TO DOWNLOAD FREEWARE?
AND ALSO i WOULD LIKE TO KNOW WHICH TOOLS ACCEPT EVeRY FPGA´s.

regards

JLuis

 

[Just an Illusion]

Hi Klejmann,

That is normal that stall don't take into account in your process,
firstly because it is not into the list of sensitivity, secondly because
you have design a flip-flop (with asynchronous reset), with a mux
controlled by 'stall' in front of it.

I'll suppose that you control register is D_Register_WB & D_Register_M &
D_Register_EX, don't it ?

Do you need that 'stall' interpretation was synchronous ? either you
can do that:

reset_async <= stall or reset;

pipeline: process (clock, reset_async)
begin

if reset_async = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
end if;
end process;

-------------------

For synchronous, the code is better like

pipeline: process(clock, reset)
begin
if reset = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
if (stall = '0') then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
else
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";
end if;
end if;
end process;

It is less confusing, but that not change your problem, because you need
wait a rising edge on clock to change the values of D_Register_WB &
D_Register_M & D_Register_EX.
Problem come from the 'time' of stall generation: if at least on between
'id_ex_memread', 'register_rs' and 'register_rt' is synchronize by
'clock', then 'stall' change 'after' the rising edge of this
synchronized signal. And in pipeline process, the value is always the
old one, when process is awake by 'clock' event.
At next 'clock' rising edge, if nothing change the 'stall' value
(before), you have your expected value.

SeeYa,
JaI

Klejmann wrote:

Hi,

I'm a beginner in VHDL but want to build in a stall logic in the mips
(pipelined Risc processor) that indicates a LW/SW Hazard.
I thougt this problem could be solved with a stall logic like that:
----------------------------------------------------------------------------
------
stall <= '1'
when (id_ex_memread = '1' AND ((register_rs = d_register_rt) OR (register_rt
= d_register_rt))) else '0';
----------------------------------------------------------------------------
-----
register_rs, register_rt are outputs from the ifetch-stage,
d_register_rt is an output from the execute-stage

My problem is, that if a stall appears, the control register must be set to
zero.
I thought a process like that would solve the problem:

pipeline: process(clock, reset)
begin
if reset = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
if (stall = '0') then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
end if;

if (stall = '1') then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";
end if;
end if;
end process;

Unfortunatly the stall - change will appear in the next clock cycle and not
in the active one.
Does anyone knows a solution to clear the control-register in the same
clock-cycle??

thx
Christian Klejmann

 

[Mike Treseler]

Weng Tianxiang wrote:

I would like to show you with real code in my PCI-CORE why it is very
important to introduce "if..orif..endif" keywords into VHDL to clear
any confusions about mutual exclusive conditions.

Any comments special to the above example are welcome.

see:
http://groups.google.com/groups?q=overlapping+cases+priority+hinze

-- Mike Treseler

 

[roller]

"Weng Tianxiang" <wtx@umem.com> escribió en el mensaje
news:511e4538.0406181434.3f57396f@posting.google.com...

I would like to show you with real code in my PCI-CORE why it is very
important to introduce "if..orif..endif" keywords into VHDL to clear
any confusions about mutual exclusive conditions.

right, cause you're the only one who actually need it...

snip

Any comments special to the above example are welcome.

Weng

yes, it's never late to learn...
i cant believe this issue is still being discussed while several solutions
were showed to be feasible...

 

[roller]

"Weng Tianxiang" <wtx@umem.com> escribió en el mensaje
news:511e4538.0406170916.c8548f5@posting.google.com...

Sorry roller, but while I agree that adding these keywords is a bad
idea, it *is* true there are optimization benefits to it.

"bad idea?", why? for beginners? I just use 30% of VHDL structures and
never pay attention to what I have never used.

and maybe you should...because "case" didnt seem to fit in your 30%

It is not a little benefit. My experiences told me that when I was
failing the final running frequency, either 66MHz for PCI or 133MHz
for PCI-X, the only way that helps me is to try to use more case
statements to reduce number of levels in "if..elsif..elsif..endif"
structure.

"if..elsif..elsif..endif" structure is Fortran language's product.

man, VHDL comes from ADA...and the need for "if...endif" is to give
priority, whether Fortran, C and every other language uses it or not is not
the issue here.

In software, there is no impact on performance, everything must be
executed in serial order. But in hardware, its essence is concurrent
implementation.

and it was showed that could be achieved without new keywords...

"if..orif..orif..endif" structure provides a similar, but excellent
structure to supplement "if..elsif..elsif..endif" structure: either in
serial implementation area or in concurrent implementation area.

whatever man

> Weng

 

[roller]

"Weng Tianxiang" <wtx@umem.com> escribió en el mensaje
news:511e4538.0406141421.3bd18c62@posting.google.com...

1. What I said is if "orif"/"ofels"/"errels" are adapted as new key
words in VHDL, it can let users use it and "IT WILL GENERATE LOGIC SO
EFFICIENT AND FAST THAT IT IS SIMILAR TO CASE STATEMENT".

Do you know "case" statement is the most efficient and fastest
statement in VHDL?

2. "there was no logic change."
It means the following:
If you write statements:
if(A1) then
NextState <= S1;
elsif(A2) then
NextState <= S2;
elsif(A3) then
NextState <= S2;
end if;

then it can be changed in the following way to add mutually exclusive
conditions:
if(A1) then
NextState <= S1;
orif(A2) then
NextState <= S2;
orif(A3) then
NextState <= S2;
end if;

That's it. "NO OTHER LOGIC CHANGE" and it will give you saving!!!

Weng

whatever you say dude

 

[Allan Herriman]

On 20 Jun 2004 23:34:29 -0700, chirag_kpp@indiatimes.com (Gopi) wrote:

Hello Everyone,
I am doing some programing in VHDL. I want to write a VHDL program
that accept ethernet frame and convert it to PPP frame (point to point
protocol). So how can i do that and If anyone has any idea regarding
the related stuffs where i can get some information.

PPP:
http://www.ietf.org/rfc/rfc1661.txt

Regards,
Allan.