How to write a VHDL code for 1Hz signal?

On Jan 8, 11:12 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Vagant wrote:
Thank you. I just wonder where I could get a complete listing (which
includes 'entity' part)?

Do you have a text editor?
Didn't the board come with some examples?

Here's a related example including an entity:http://home.comcast.net/~mike_treseler/count_enable.vhd

        -- Mike Treseler
No, it's not what I am asking about.
 
V

Vagant

Guest
Hello,

I am a newbie to VHDL programming and want to test my FPGA board with
a code which lights a LED every second. To do this I need a VHDL code
for 1 Hz signal generator. Unfortunately, I cannot find such in Web.
Also I am not experienced in VHDL programming and not sure how to
write such a code. If you have any similar code could you put it in
this thread, please or give me some idea how to write this. I also
wonder - is it necessary to use a clock for such signal generator?
 
Vagant schrieb:

I am a newbie to VHDL programming and want to test my FPGA board with
a code which lights a LED every second. To do this I need a VHDL code
for 1 Hz signal generator. Unfortunately, I cannot find such in Web.
Take your clock (which is running at X MHz) and divide it by X.


process(reset_n,clk)
variable cnt : integer;
begin
if (reset_n='0') then
clk_out<='0';
cnt:=0;
elsif rising_edge(clk) then
if (cnt=divider_half-1) then
clk_out<=NOT(clk_out);
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;

Note that divider_half is X/2.

The code is not tested - just written in the mail program.

Ralf
 
On Jan 8, 10:22 pm, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:
Vagant schrieb:

I am a newbie to VHDL programming and want to test my FPGA board with
a code which lights a LED every second. To do this I need a VHDL code
for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

Take your clock (which is running at X MHz) and divide it by X.

process(reset_n,clk)
variable   cnt   : integer;
begin
if (reset_n='0') then
        clk_out<='0';
        cnt:=0;
elsif rising_edge(clk) then
        if (cnt=divider_half-1) then
                clk_out<=NOT(clk_out);
                cnt:=0;
        else
                cnt:=cnt+1;
        end if;
end if;
end process;

Note that divider_half is X/2.

The code is not tested - just written in the mail program.

Ralf
Thank you. I just wonder where I could get a complete listing (which
includes 'entity' part)?
 
Vagant wrote:

Thank you. I just wonder where I could get a complete listing (which
includes 'entity' part)?
Do you have a text editor?
Didn't the board come with some examples?

Here's a related example including an entity:
http://home.comcast.net/~mike_treseler/count_enable.vhd

-- Mike Treseler
 
On Jan 8, 10:22 pm, Ralf Hildebrandt <Ralf-Hildebra...@gmx.de> wrote:
Take your clock (which is running at X MHz) and divide it by X.

I guess it should be divided by X*10^6 to get 1 Hz, isn't it?
 

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