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[gallen]

Static Timing Analysis.

It's nearly impossible to prove that a design will work with
simulation. Static Timing Analysis is a simulation-less proof
mechanism. The tool uses clock periods and setup and hold times and
propagation delays of the hardware to prove it a design will meet a
specified timing.

A digital design flow should go basically like this:
1. Specify and make list of features.
2. Implement RTL.
3. Write functional simulations to test features exhaustively.
4. Test features.
5. Write design constraints.
6. Synthesize.
7. Run Static Timing.
8. Do timing fixes if necessary, go back to step 4.
9. Tape out or do whatever you need to do with your complete design.

The point is you should never need to run timing sims. That said, I've
never worked on a chip that didn't need them. All I can say is that
you almost can't guarantee a circuit to be working through timing gate
sims.

-Arlen
GaLaKtIkUs™ wrote:

Mike Treseler wrote:
GaLaKtIkUs™ wrote:
Rewrite the whole libraries, which model Xilinx primitives for all
Xilinx FPGA/CPLD families and all speed grades?

No.
Leave the primitives to synthesis.
Leave the timing to STA.

STA?


-- Mike Treseler