How to detect the posedge of two different clocks at the sa

[Sriram]

Hi,
I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of differnt frequencies.

code something like this...

fork
@posedge clkA
begin
a=$time
end
@posedge clkB
begin
b=$time
end
join

if (a=b) then some code.....


this code may work for simulation but if i want some synthesizable hardware logic
whatelse can i use. please help me out.


thanks in advance..
Sriram.

 

[GaborSzakacs]

Sriram wrote:

Hi,
I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of differnt frequencies.

code something like this...

fork
@posedge clkA
begin
a=$time
end
@posedge clkB
begin
b=$time
end
join

if (a=b) then some code.....


this code may work for simulation but if i want some synthesizable hardware logic
whatelse can i use. please help me out.


thanks in advance..
Sriram.
In real hardware you can at best find the edge coincidence within a

particular window of time, based on your ability to measure arrival
time. If you were doing this starting with transistors, you could
possibly come up with two circuits that create a very narrow pulse
after the posedge of each clock and then AND them together to trigger
your startup.

--
Gabor

 

On Thursday, June 13, 2013 11:41:27 PM UTC-7, Sriram wrote:

Hi,
I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of differnt frequencies.
code something like this...
fork
@posedge clkA
begin
a=$time
end
@posedge clkB
begin
b=$time
end
join

What you need is either a phase detector or a time to digital converter depending on what you are really trying to accomplish. Either function is difficult implement in a purely digital fashion. Also expecting to resolve the error you are generating to an exact zero is not something you can accomplish. You can create a circuit which can on a statistical basis tell you that the edges of two clocks are within a certain window the width of which depends on temperature, process etc. Search for "phase detector" and "time to digital conversion/converter".

 

[Sriram]

On Friday, June 14, 2013 7:43:15 PM UTC+5:30, gabor wrote:

Sriram wrote: > Hi, > I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of differnt frequencies. > > code something like this... > > fork > @posedge clkA > begin > a=$time > end > @posedge clkB > begin > b=$time > end > join > > if (a=b) then some code..... > > > this code may work for simulation but if i want some synthesizable hardware logic > whatelse can i use. please help me out. > > > thanks in advance.. > Sriram. In real hardware you can at best find the edge coincidence within a particular window of time, based on your ability to measure arrival time. If you were doing this starting with transistors, you could possibly come up with two circuits that create a very narrow pulse after the posedge of each clock and then AND them together to trigger your startup. -- Gabor

Hi Gabor,
thanks for ur response.I am a beginner for verilog and i am trying to have this design atleast at the gate level.Is there any way to design this at the gate level considering some small window of time difference between the arriavl of two clks.
--Sriram

 

[Sriram]

On Sunday, June 16, 2013 5:04:23 AM UTC+5:30, muzaff...@gmail.com wrote:

On Thursday, June 13, 2013 11:41:27 PM UTC-7, Sriram wrote: > Hi, > I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of differnt frequencies. > code something like this... > fork > @posedge clkA > begin > a=$time > end > @posedge clkB > begin > b=$time > end > join What you need is either a phase detector or a time to digital converter depending on what you are really trying to accomplish. Either function is difficult implement in a purely digital fashion. Also expecting to resolve the error you are generating to an exact zero is not something you can accomplish. You can create a circuit which can on a statistical basis tell you that the edges of two clocks are within a certain window the width of which depends on temperature, process etc. Search for "phase detector" and "time to digital conversion/converter".

Hi, thanks for ur response.I can understand that resolving this error to zero is not easy.My design doesnt require resolving the error. It is like i have to start the process on detecting the first coincidence of rising edges..(not exact but with some small window width).It goes like this... two clocks running at two different frequencies say in 3:2 ratio are used and a process of my design should be triggered at some point where two rising edges match and then it should give some error in form of an led incase the frequencies get change later.
---Sriram

 

If you do not care too much about timing, but just the behavior, how about the following? Not compiled, so use with caution.

module simul_posedge (
input wire clkA
, input wire clkB

, output wire detected_simul_posedges
);
parameter MAX_COUNTER_WIDTH = 64; // or 128 or ...
parameter DETECTED_SIMUL_POSEDGES = 1000; // depends on frequency of veryHighSpeedClk

reg [MAX_COUNTER_WIDTH-1:0] counter;
wire clkC;

assign clkC = clkA^clkB;

always @(posedge veryHighSpeedClk) begin
if (~clkC)
counter <= 'b0;
else
counter <= counter + 1'b1;
end

assign detected_simul_posedges = (counter >= DETECTED_SIMUL_POSEDGES);

endmodule

 

[Richard Damon]

On 6/14/13, 2:41 AM, Sriram wrote:

Hi, I am working on a design which should detect the first match of
two rising edges of two asynchronous clocks of differnt frequencies.

My first though is if your answer requires detecting two simultaneous
edges of asynchronous clocks, you either have the wrong answer or the
wrong question.

In exactitude, it will never happen, and in real approximation, it is so
fuzzy as to be unreliable, as you are basically asking for the system to
be close to meta-stable and then detect this.

 

[rickman]

On 6/18/2013 11:36 PM, Sriram wrote:

On Sunday, June 16, 2013 5:04:23 AM UTC+5:30, muzaff...@gmail.com wrote:
On Thursday, June 13, 2013 11:41:27 PM UTC-7, Sriram wrote: > Hi, > I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of differnt frequencies. > code something like this... > fork > @posedge clkA > begin > a=$time > end > @posedge clkB > begin > b=$time > end > join What you need is either a phase detector or a time to digital converter depending on what you are really trying to accomplish. Either function is difficult implement in a purely digital fashion. Also expecting to resolve the error you are generating to an exact zero is not something you can accomplish. You can create a circuit which can on a statistical basis tell you that the edges of two clocks are within a certain window the width of which depends on temperature, process etc. Search for "phase detector" and "time to digital conversion/converter".

Hi, thanks for ur response.I can understand that resolving this error to zero is not easy.My design doesnt require resolving the error. It is like i have to start the process on detecting the first coincidence of rising edges.(not exact but with some small window width).It goes like this... two clocks running at two different frequencies say in 3:2 ratio are used and a process of my design should be triggered at some point where two rising edges match and then it should give some error in form of an led incase the frequencies get change later.
---Sriram

You have started to explain your real need, but I don't completely
understand yet. I recommend that initially you don't even think about
the issue of how to implement your solution in Verilog since you first
have to understand the problem before you can even begin to understand
the solution. Instead you might want to explain the problem in a way
that doesn't even consider the solution at all. Then maybe we will
understand the problem enough to help you.

I don't understand what you are really trying to measure. At first you
say you want to detect the coincidence of two clock rising edges. Then
you say you want to detect when two clock frequencies change. So what
are you really trying to do?

I'm will to bet the solution to your real problem does not involve
detecting coincidence of clocks at all.

--

Rick