How do I make dual-port RAM from single port RAM?

[Frank]

<sharp@cadence.com> wrote in message
news:1141236232.823214.283550@j33g2000cwa.googlegroups.com...

That is a clever solution that I hadn't thought of. Of course, your
VALID_BIT array needs the capabilities of a true dual-port memory. So
this doesn't really build a dual-port memory just out of RAMs. It
builds it from 4 RAMs and a smaller dual-port memory (just as many
elements, but only 1 bit wide). You would have to build that smaller
dual-port memory out of flip-flops. The result still might be smaller
than building the full-size memory out of flip-flops.

Morning Samuelsson & sharp, I haven't got time to study the sequence of the
clever
solution yet. I want to know is, does it have the function of a full dual
port R/W RAM
if the R/W accesses of both ports are random? My RAM is 130*6bit, and the IP
uses
eight pieces of this RAM.

TIA

 

Yes, Ulf's solution gives full dual-port functionality for arbitrary
addresses (though of course you have to decide which port gets the last
word in case of simultaneous writes to the same address, as with any
dual-port memory).

But with your small word size of 6 bits, this may not be
cost-effective. The VALID_BIT array requires similar logic to a
1-bit-wide dual-port memory (not quite the same, since port 0 always
writes a value of 0 and port 1 always writes a value of 1). So you
have to design something close to a 130*1bit dual-port memory out of
flip-flops and logic, and use that with four 130*6bit RAMs (or two
130*6bit dual-read/single-write RAMs, since you indicated you have
those). You might be as well off to design a 130*6bit dual-port memory
from flip-flops and logic.

 

[Kim Enkovaara]

Peter Alfke wrote:

Sounds like a powerful FPGA argument:
Ifyou really need a true dual-port memory (read and write from either
or both ports simultaneously), you are out-of-luck in the ASIC world,
but you can do this just fine in FPGAs.
Nice to know we have such an edge...

That is completely dependent on the ASIC libraries. In FPGA you are out of
luck with higer amount of ports that are available in some ASIC libraries.
For example in the ASIC library I use there are: single port, 1 read 1 write,
dual port and 4-port memories. And then different versions of those
(density, power, speed).

--Kim

 

[Derek Simmons]

I haven't had time to load Xilinx's tools (sometime I'm going to have
to do it for another project) to see what there DPRAM library device
looks like.

The solution I was going to offer was going to be a time division
solution like rhnlogic suggested. Relative to the reading/writing of
the ports of the DPRAM, what clocks are available? What other controls
signals are present that could be taken advantage of?

If you want to reinvent the wheel you could implement your own dual
port memory. It would probably be a little bit more than 6240 flip
flops if you can limit the address to 130 range and if you're sloppy
about it 16384 flip flops for the whole 256 range. (plus addressing and
control support)

Derek

 

When you wrote PortA address 17, you wrote into address 17 of RAM0 and
RAM1. You also wrote 0 (meaning A is valid) into address 17 of
VALID_BIT. When you read PortB address 17, you read address 17 of RAM1
and RAM3. You also read address 17 of VALID_BIT, which gives you back
0, telling you to select the output of RAM1. This gives you the value
you just wrote to RAM1 when you wrote to PortA address 17.

If you had written to address 17 via PortB last, then address 17 of
VALID_BIT would have been set to 1, telling you to select the output of
RAM3 instead. This would have been correct, since a write to portB
would have written to RAM2 and RAM3. If you read portA address 17, you
will read address 17 of RAM0 and RAM2 instead, and selected between
those based on VALID_BIT.

Or perhaps what you are missing is that each of these RAMs has a read
port and a write port, which can be used simultaneously with
independent addresses. This was one of the components that was
described as being available. So PortB can be reading address 17 of
RAM1 at the same time PortA is writing address 22 of RAM1.

 

Another clever solution. This requires the same amount of RAM as Ulf's
scheme, but without requiring the 2Rd/2Wr VALID_BIT array. However, it
may require a longer write cycle time, to allow completing the
associated read and XOR with enough setup time for the write. But part
of the write can overlap the read, so it should still be faster than
the time-multiplexing approaches.

 

[John_H]

sharp@cadence.com wrote:

Another clever solution. This requires the same amount of RAM as Ulf's
scheme, but without requiring the 2Rd/2Wr VALID_BIT array. However, it
may require a longer write cycle time, to allow completing the
associated read and XOR with enough setup time for the write. But part
of the write can overlap the read, so it should still be faster than
the time-multiplexing approaches.

What I did forget is that the memory may be synchronous read and write.
If the read is asynchronous then this method still works but youre
comment on timing is well taken. In the FPGA there's a nice, small
setup time for memory address and data. An asynchronous read would
require the address access time before that XOR. If the translation is
from FPGA to ASIC, there may be enough margin in the timing to specify
the read access and XOR from the address and the XOR alone from the data
before the write strobe.

If the ASIC memory is synchronous read without the async data, this
method would require more RAMs and some feedback to account for
just-written addresses.

Is the memory 1Wr/2Rd memory primitive an asynchronous read?

 

[Frank]

<sharp@cadence.com> wrote in message
news:1141235829.504003.89220@z34g2000cwc.googlegroups.com...

Presumably this depends on what ASIC libraries you have. There is no
inherent reason that an ASIC library could not include dual-port
memories. Apparently the original poster's didn't.

True, some TSMC ASIC libraries had dual-read/write memories, and they used
to provide
memory generators which enables creating the memory blocks of any capacity.

After we changed foundry, things got really complicated. In the new library,
only a few memories
are provided and the width & depth are also fixed. It becomes very
inefficient to use these RAMs.

I guess I am out of luck on memory issues this time.

 

[Frank]

"Derek Simmons" <dereks314@gmail.com> wrote in message
news:1141230364.062159.31900@i39g2000cwa.googlegroups.com...

I've been trying to follow your problem and now have time to lend some
help. I'm going to approach this from a black-box design point of view.


First question is how are in implementing it or what language are you
using (VHDL, Verilog or something else)?

What size device are you looking to create (data and address bus
width)? Or are you trying to create a library device?

What device and signals in the original design being used?

Derek

Thank you Derek.
I received an FPGA design in RTL Verilog and need to convert into ASIC. Now
everything is done except this memory issue. The design of the RTL is
unfamiliar to
me so large modifications are meant only for the long run. Requesting
redesign of
the memory isn't an option either.

The culprit RAMs are 8 instances of 130*6bit DPRAM. My entire design is 200K
gate without RAM. My short term goal is to use the existing RAMs in the ASIC
library and perform successful synthesis & gate level simulation, with ASIC
RAMs
included in the system (I could simulate with Xilinx RAM and ASIC for the
rest).

What ideas do you have for my description?

 

[JJ]

130 by 6 is pretty tiny to have used a whole 4K or 18k bit DPRAM but
the DP feature makes it a job already done.

Are the 8 rams independant copies of the same DP R/W design?
And 130 is a bit odd isn't it?

For this size of this problem the 4 way Ulf design doesn't look so bad
assuming you can compile 130 by 6 arrays, I'd imagine they will be
bigger. Now you only need 130 DP flags to resolve valid words.

John

 

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Frank @ CN wrote:

Hi, there:

In my application, a RAM needs to be written/read from two sets of
data/address ports
simultaneously. However, in the ASIC library I can only instantiate some
single port RAM
and RAM which can be written in one port and read from the other port.

How shall I solve this problem?

Thank you.

 

What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
komal@priorityoneindia.com ASAP. Kindly inform the same to your
colleagues and friends.



Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: komal@priorityoneindia.com



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Michael Schöberl wrote:

In my application, a RAM needs to be written/read from two sets of
data/address ports simultaneously.

estimate your worst case data rates and take a ram with
the sum of these data-rates (plus overhead) ...

then you need to build some logic to switch between
Port A and B to transfer concurrent access to a
sequential access scheme


bye,
Michael

 

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John_H wrote:

Frank @ CN wrote:
Hi, there:

In my application, a RAM needs to be written/read from two sets of
data/address ports
simultaneously. However, in the ASIC library I can only instantiate some
single port RAM
and RAM which can be written in one port and read from the other port.

How shall I solve this problem?

Thank you.

You might get a better idea of the particulars by looking at a data
sheet for IDT dual-port memories. (www.idt.com)

 

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cell libraries.
Experienced in full custom design and layout.
Knowledge of the cell characterization process.
Basic understanding of silicon processing technology.
Understanding of place and route tools, and how they work.
Comfortable with the Linix operating system and strong programming
skills in perl.
Experience working with silicon foundries, preferably TSMC.
Full understanding of the following IC Design tools:
HSPICE
Verilog logic simulation
Cadence Composer
Cadence Virtuoso
Synopsys Design Compiler
A proven track record of successful design projects - completed on
schedule.
Excellent communication skills.
Leadership skills and a personal commitment to the team's success are
also required attributes
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[Josep Durán]

"Ulf Samuelsson" <ulf@a-t-m-e-l.com> escribió en el mensaje
news:du3dop$cq1$1@emma.aioe.org...

You can instantiate FOUR rams and implement a valid bit for each location
in a register.
PortA can write to RAM0,RAM1 and read from RAM0 and RAM2
PortB can write to RAM2,RAM3 and read from RAM1 and RAM3

When PortA writes to address position 17, both RAM0[17] and RAM1[17] are
updated and the
VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of
RAM2,3.

When PortB reads address position 17, both RAM1 and RAM3 are read.
A multiplexer on the output is controlled by the selected VALID_BIT,
and since VALID_BIT[17] is zero, it will select the output of RAM1 over
RAM3.

Obviously this is going to use some gates,so it is not practical for large
SRAMs.
Running the RAM at 2 x frequency is going to cost a lot less.

Following the previous example, I fail to see how can I read PortB address
17
(last time written through portA) while PortA is writing adddress (say) 22.

Am I missing something ?



Regards

Josep Duran