S
Symon
Guest
Hi Peter,
Yeah, the home built processor is great fun. I did a Xilinx VirtexII one
when the parts first appeared and learnt a lot about the carry chain, those
FMUX thingies, and the mighty 'mult_and'! It also teaches you a lot about
the dual port block rams and multipliers. I called it nanoblaze, kind of
halfway between Micro and Pico, because it used about 250 LUTs, 16 bits, 16
GP regs in a LUT RAM file, stack and program in a block ram, multiply
instruction with the hard multiplier. If you target a particular
architecture you can get suprisingly good performance, I got ~90MIPS in a
VirtexII-slowestgrade, non-pipelined, i.e. 1 clock per most instructions
including conditional relative jumps. Even single cycle interrupts!
Once again, as you can tell(!!), I found it great fun, and an excellent
way to learn about the fabric of the FPGA. Also, can teach you a lot about
floorplanning and performance optimisation. I also used it to learn PERL to
write the assembler, which was probably the best thing to come out of the
whole project! BUT... I'd almost certainly NOT use it in a commercial
product, too much documentation involved and soon every FPGA will have a
hard processor anyway.
Good luck, Syms.
"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bosgmt$n0i$1@cesium.transmeta.com...
Yeah, the home built processor is great fun. I did a Xilinx VirtexII one
when the parts first appeared and learnt a lot about the carry chain, those
FMUX thingies, and the mighty 'mult_and'! It also teaches you a lot about
the dual port block rams and multipliers. I called it nanoblaze, kind of
halfway between Micro and Pico, because it used about 250 LUTs, 16 bits, 16
GP regs in a LUT RAM file, stack and program in a block ram, multiply
instruction with the hard multiplier. If you target a particular
architecture you can get suprisingly good performance, I got ~90MIPS in a
VirtexII-slowestgrade, non-pipelined, i.e. 1 clock per most instructions
including conditional relative jumps. Even single cycle interrupts!
Once again, as you can tell(!!), I found it great fun, and an excellent
way to learn about the fabric of the FPGA. Also, can teach you a lot about
floorplanning and performance optimisation. I also used it to learn PERL to
write the assembler, which was probably the best thing to come out of the
whole project! BUT... I'd almost certainly NOT use it in a commercial
product, too much documentation involved and soon every FPGA will have a
hard processor anyway.
Good luck, Syms.
"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bosgmt$n0i$1@cesium.transmeta.com...