HI all please sort it out problem about block ram in verilog

[m2star]

i use this code for memory of my project its working for modelsim but
not working for ise-9.1i
is there any other technique for this purpose.....................
"module blockram(clk, RW, address, Din, Dout);
input clk,RW;
input [11:00] address;
input [15:00] Din;
output [15:00] Dout;
reg [15:00] Dout;

reg [15:0] mem[0:15]; //declare memory
initial
begin
mem[0] = 16'h100a; mem[1] = 16'h200d; mem[2] = 16'h300c;
mem[3] = 16'h9005; mem[4] = 16'h300b; mem[5] = 16'h400d;
mem[6] = 16'h8800; mem[7] = 16'h7000; mem[8] = 16'h300a;
mem[9] = 16'h7000; mem[10] = 16'h5e93; mem[11] = 16'h372a;
mem[12] = 16'h56d3; mem[13] = 16'h7000; mem[14] = 16'h7000;
mem[15] = 16'h7000;// mem[15] = 16'h7000;
end
always @(posedge clk)
begin
if (!RW)
mem[address] <= Din; //(RW=0)write into memory
Dout <= mem[address]; //(RW=1)read from memory
end
endmodule"

 

[gabor]

On Friday, March 4, 2011 7:32:39 AM UTC-5, m2star wrote:

i use this code for memory of my project its working for modelsim but
not working for ise-9.1i
is there any other technique for this purpose.....................
"module blockram(clk, RW, address, Din, Dout);
input clk,RW;
input [11:00] address;
input [15:00] Din;
output [15:00] Dout;
reg [15:00] Dout;

reg [15:0] mem[0:15]; //declare memory
initial
begin
mem[0] = 16'h100a; mem[1] = 16'h200d; mem[2] = 16'h300c;
mem[3] = 16'h9005; mem[4] = 16'h300b; mem[5] = 16'h400d;
mem[6] = 16'h8800; mem[7] = 16'h7000; mem[8] = 16'h300a;
mem[9] = 16'h7000; mem[10] = 16'h5e93; mem[11] = 16'h372a;
mem[12] = 16'h56d3; mem[13] = 16'h7000; mem[14] = 16'h7000;
mem[15] = 16'h7000;// mem[15] = 16'h7000;
end
always @(posedge clk)
begin
if (!RW)
mem[address] <= Din; //(RW=0)write into memory
Dout <= mem[address]; //(RW=1)read from memory
end
endmodule"

Nothing obviously wrong, but XST is a bit picky
about what it will infer memory from. When you
say it doesn't work, do you mean that you get
errors, or just that it doesn't actually infer
RAM?

Also I noticed you only have 15 memory elements but
use a 12 bit address. This is the sort of thing that
gives problems when trying to infer memory from a
standard "template." When all fails, you can go
through the "language templates" in ISE to see
how xilinx recommends writing code to infer RAM.

-- Gabor

 

[m2star]

On Mar 5, 8:19 am, gabor <ga...@alacron.com> wrote:

On Friday, March 4, 2011 7:32:39 AM UTC-5, m2star wrote:
i use this code for memory of my project its working for modelsim but
not working for ise-9.1i
is there any other technique for this purpose.....................
"module blockram(clk, RW,     address, Din, Dout);
input              clk,RW;
input      [11:00] address;
input      [15:00] Din;
output     [15:00] Dout;
reg        [15:00] Dout;

reg [15:0] mem[0:15];                      //declare memory
initial
   begin
           mem[0]  = 16'h100a;     mem[1]  = 16'h200d; mem[2]      = 16'h300c;
           mem[3]  = 16'h9005;     mem[4]  = 16'h300b; mem[5]      = 16'h400d;
           mem[6]  = 16'h8800;     mem[7]  = 16'h7000; mem[8]      = 16'h300a;
           mem[9]  = 16'h7000;       mem[10]       = 16'h5e93; mem[11]     = 16'h372a;
           mem[12] = 16'h56d3;       mem[13]       = 16'h7000; mem[14]     = 16'h7000;
           mem[15] = 16'h7000;//   mem[15] = 16'h7000;
   end
always @(posedge clk)
begin
   if (!RW)
           mem[address] <= Din;                 //(RW=0)write into memory
   Dout    <= mem[address];                             //(RW=1)read from memory
end
endmodule"

Nothing obviously wrong, but XST is a bit picky
about what it will infer memory from.  When you
say it doesn't work, do you mean that you get
errors, or just that it doesn't actually infer
RAM?

Also I noticed you only have 15 memory elements but
use a 12 bit address.  This is the sort of thing that
gives problems when trying to infer memory from a
standard "template."  When all fails, you can go
through the "language templates" in ISE to see
how xilinx recommends writing code to infer RAM.

-- Gabor

hi i don't get errors instead i realize that its not being filled as i
put values in each index ...........
i decrease the size of my memory indexes because it take lot of time
in synthesizing full memory of 16bit-x-4k using ISE-9.1i
i am filling it now using .coe file but i want to use this method as
mentioned above and i will try your suggestions...........
thanks for help...................

 

[gabor]

On Saturday, March 5, 2011 2:30:52 PM UTC-5, m2star wrote:

hi i don't get errors instead i realize that its not being filled as i
put values in each index ...........
i decrease the size of my memory indexes because it take lot of time
in synthesizing full memory of 16bit-x-4k using ISE-9.1i
i am filling it now using .coe file but i want to use this method as
mentioned above and i will try your suggestions...........
thanks for help...................

It's possible that XST 9.1 doesn't actually implement
initial blocks. I know that you can use initial
blocks in later versions, though including 10.1

I have also seen problems with XST and partially
initialized memory arrays. Usually you get a
warning like "<some_array> partially initialized
initialization data will be ignored." I have
seen this for example when using $readmemh or
$readmemb in an initial block when the data
file did not have exactly the same number of
elements as the array. By the way, for larger
RAMs, using an external file and $readmemh is
the preferred method for inference. Obviously
you can use CoreGen and a .coe file as a workaround
if you can't get the inferred memory to initialize
in XST 9.1

Regards,
Gabor