Help on un-supported allocator and '.all'

[fl]

Hello,

I am still new to VHDL. Now two questions pop up from an example code snippet.
See below please.

The first question is about 'new' allocator. It looks like Xilinx Vivado does
not support it (it has an error of the line headed with 'string_v...'

My second question is about '.all'. I know string_v is an access type. I
don't find the answer of '.all'.

Could you help me on the two questions?


Thanks,


/////////////////////////////
procedure verify is
type string_p is access string;
variable string_v : string_p;
begin
string_v := new string'(integer'image(to_integer(expect_v)));
report "___Step " & integer'image(step_v);
.........
ck : if match_v then
boring : if verbose_g then
report "____________ saw " & string_v.all & " as expected";
end if boring;

 

[fl]

On Friday, December 15, 2017 at 8:43:53 PM UTC-5, fl wrote:

Hello,

I am still new to VHDL. Now two questions pop up from an example code snippet.
See below please.

The first question is about 'new' allocator. It looks like Xilinx Vivado does
not support it (it has an error of the line headed with 'string_v...'

My second question is about '.all'. I know string_v is an access type. I
don't find the answer of '.all'.

Could you help me on the two questions?


Thanks,


/////////////////////////////
procedure verify is
type string_p is access string;
variable string_v : string_p;
begin
string_v := new string'(integer'image(to_integer(expect_v)));
report "___Step " & integer'image(step_v);
........
ck : if match_v then
boring : if verbose_g then
report "____________ saw " & string_v.all & " as expected";
end if boring;

Excuse me. I want to make it clear here.
I want to know whether there is a way to replace the code having 'new'
to make it work in Vivado?

I have browsed through VHDL tutorial on allocator, but I am still unclear
about the reason to use 'new'. Just as the above said, can we use an
alternative way making it work?


Thanks again,

 

[Rob Gaddi]

On 12/15/2017 05:52 PM, fl wrote:

On Friday, December 15, 2017 at 8:43:53 PM UTC-5, fl wrote:
Hello,

I am still new to VHDL. Now two questions pop up from an example code snippet.
See below please.

The first question is about 'new' allocator. It looks like Xilinx Vivado does
not support it (it has an error of the line headed with 'string_v...'

My second question is about '.all'. I know string_v is an access type. I
don't find the answer of '.all'.

Could you help me on the two questions?


Thanks,


/////////////////////////////
procedure verify is
type string_p is access string;
variable string_v : string_p;
begin
string_v := new string'(integer'image(to_integer(expect_v)));
report "___Step " & integer'image(step_v);
........
ck : if match_v then
boring : if verbose_g then
report "____________ saw " & string_v.all & " as expected";
end if boring;

Excuse me. I want to make it clear here.
I want to know whether there is a way to replace the code having 'new'
to make it work in Vivado?

I have browsed through VHDL tutorial on allocator, but I am still unclear
about the reason to use 'new'. Just as the above said, can we use an
alternative way making it work?


Thanks again,

I haven't tried using the Vivado simulator very much, but let me get the
obvious question out of the way: You are talking about the simulator,
not synthesis right?

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

 

[fl]

On Friday, December 15, 2017 at 8:58:49 PM UTC-5, Rob Gaddi wrote:

On 12/15/2017 05:52 PM, fl wrote:
On Friday, December 15, 2017 at 8:43:53 PM UTC-5, fl wrote:
Hello,

I am still new to VHDL. Now two questions pop up from an example code snippet.
See below please.

The first question is about 'new' allocator. It looks like Xilinx Vivado does
not support it (it has an error of the line headed with 'string_v...'

My second question is about '.all'. I know string_v is an access type. I
don't find the answer of '.all'.

Could you help me on the two questions?


Thanks,


/////////////////////////////
procedure verify is
type string_p is access string;
variable string_v : string_p;
begin
string_v := new string'(integer'image(to_integer(expect_v)));
report "___Step " & integer'image(step_v);
........
ck : if match_v then
boring : if verbose_g then
report "____________ saw " & string_v.all & " as expected";
end if boring;

Excuse me. I want to make it clear here.
I want to know whether there is a way to replace the code having 'new'
to make it work in Vivado?

I have browsed through VHDL tutorial on allocator, but I am still unclear
about the reason to use 'new'. Just as the above said, can we use an
alternative way making it work?


Thanks again,


I haven't tried using the Vivado simulator very much, but let me get the
obvious question out of the way: You are talking about the simulator,
not synthesis right?

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

Thanks. You are right. The simulation code may not be put in the design part.