HDL simple survey - what do you actually use

[Kevin Neilson]

use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.

Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim.

I do not think the Palnitkar book is good and I have never found any Verilog book that is very good. I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms.

 

[rickman]

Kevin Neilson wrote on 1/16/2018 8:33 PM:

use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.

Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim.

In VHDL everything is explicitly stated, no assumptions. In Verilog my
understanding is there are things that are assumed that you need to know
about or the tools will do something other than what you expect. It is not
possible to test everything, so some of these may be missed unless you are
wary of them. I don't recall anything about them, but I think some have to
do with arithmetic. In VHDL you specify the bus widths of operands, results
and even intermediates. I believe Verilog is consistent, but what it does
may not be obvious.


> I do not think the Palnitkar book is good and I have never found any Verilog book that is very good.

I get this a lot.

I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

[o pere o]

On 13/01/18 12:29, Thomas Heller wrote:

Am 10.01.2018 um 15:17 schrieb john:

I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other


Is use MyHDL which gets translated into VHDL for synthesis.

Thomas

I had a look at MyHDL a while ago and it looked promising. Can you share
some experiences, pointers, etc? I'd like to know from someone who
actually is using it!

Pere

 

[john p]

On Tuesday, January 16, 2018 at 6:21:06 PM UTC-8, rickman wrote:

Kevin Neilson wrote on 1/16/2018 8:33 PM:

use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.

Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim.

In VHDL everything is explicitly stated, no assumptions. In Verilog my
understanding is there are things that are assumed that you need to know
about or the tools will do something other than what you expect. It is not
possible to test everything, so some of these may be missed unless you are
wary of them. I don't recall anything about them, but I think some have to
do with arithmetic. In VHDL you specify the bus widths of operands, results
and even intermediates. I believe Verilog is consistent, but what it does
may not be obvious.


I do not think the Palnitkar book is good and I have never found any Verilog book that is very good.

I get this a lot.


I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms.



--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

I have not yet found a Verilog book that I thought was worth buying

I'd look for papers by Sutherland and Cliff Cummings, especially, I think, Cliff's book on Verilog gotchas.

The key rule I use for Verilog is when coding combinatorial blocks, use
blocking assignments:
always @(*)
foo = bar;
When coding synchronous logic, use non-blocking assignments:
always @(posedge clk)
foo <= bar;

Rules are made to be broken, but I *rarely* break these two rules.

John P

 

[Thomas Heller]

Am 17.01.2018 um 08:37 schrieb o pere o:

On 13/01/18 12:29, Thomas Heller wrote:
Am 10.01.2018 um 15:17 schrieb john:

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other


Is use MyHDL which gets translated into VHDL for synthesis.


I had a look at MyHDL a while ago and it looked promising. Can you share
some experiences, pointers, etc? I'd like to know from someone who
actually is using it!

I'm not good at writing reviews, but I'm very happy with MyHDL. It
removes the pain that I mostly feel when writing VHDL.
And using MyHDL is the first time that I write real testbenches
and simulate.

Something that I can recommend to read about MyHDL are articles by Jan
Decaluwe, the main author, at http://jandecaluwe.com/hdldesign/ .
Especially this one: http://jandecaluwe.com/hdldesign/counting.html .
Then Christopher Felton also has a couple of nice articles at
fpgarelated:
https://www.fpgarelated.com/blogs-1/nf/Christopher_Felton.php

Thomas

 

[Mark Humphries]

On Wednesday, January 10, 2018 at 10:17:32 PM UTC+8, john wrote:

I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

=========================
http://johntech.co.uk
=========================

I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around.

For a reference I recommend:
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland.

 

[rickman]

Mark Humphries wrote on 1/18/2018 10:34 AM:

On Wednesday, January 10, 2018 at 10:17:32 PM UTC+8, john wrote:
I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

=========================
http://johntech.co.uk
=========================

I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around.

For a reference I recommend:
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland.

Seems to be a $120 book. That's a bit steep even for HDL books.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

 

[Theo Markettos]

john <anon@example.com> wrote:

I'm trying to decide on which to use for a project as the main default
that may include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Bluespec SystemVerilog (BSV), which is actually nothing to do with
SystemVerilog but is a high-level HDL derived from Haskell (including types,
polymorphism, functional language features).

Since BSV is a bit niche, I teach SystemVerilog to undergrads and will use
it for glue when necessary.

Talking to major IP vendors who provide both Verilog and VHDL versions of
IP, the Verilog versions are a lot more popular.

Theo

 

[HT-Lab]

On 10/01/2018 20:29, already5chosen@yahoo.com wrote:

On Wednesday, January 10, 2018 at 7:33:10 PM UTC+2, Rob Gaddi wrote:
On 01/10/2018 06:17 AM, john wrote:
...


VHDL, for both synthesis and testbenching. Some Verilog sneaks into my
design when vendor-provided IP cores only come that way, but I'm
read-only on it.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

The same here.
And I don't believe in things like SystemC.

I do.

It is true SystemC is more for the C/C++ aficionados. However SystemC
has a lot going for it, here are some quick points:

1) You get a simulator and all the support libraries in source for free.
2) If you know VHDL then you can easily program in SystemC (same model
of signals, processes, variables, delta cycles etc). No horrible
blocking/non-blocking, wire/reg, race spaghetti.
3) It is easy to learn and you don't have to dive to deep into C++.
4) It is great for behavioural modelling.
5) You can choose from many free and commercial IDE's.
6) There is a free UVM library.
7) It runs on many platforms (you just need a C++ compiler)
8) There is a synthesisable standard (albeit somewhat outdated)
9) There are a number of SystemC translators/synthesis tools available.
10) You can "embed" the OSCI engine into your product (bar the usual
license agreement)
11) It is relative easy to bolt on any library you like Qt/SDL2.
12) It has the best TLM capabilities (SV uses the same models)
13) It has transaction recordings capabilities (SCV)
14) It has some assertion capabilities (PSL support would be great!)
15) It supports randomisation (like rand in SV) and contains a
constraint solver.

The free nature of it is both a blessing and a curse. Because it is free
commercial support is somewhat sluggish (Cadence being the exception).
There are (AFAIK) no free RTL style IDE's which works as easily as
VHDL/Verilog on Modelsim/VCS/NCSim/Riviera/etc. Using sc_trace and
GTKWave is just too painful. There are products like Vista that come
close but still not as slick as Modelsim. I tried to write something but
underestimated the amount of free time it takes to create something
barely usable.

So for pure RTL designs I agree that you can't beat good old VHDL and SV
(forget about Verilog).

To answer the OP's question, VHDL for design and
VHDL/SystemC/PSL/FLI/Tcl for testbenches. I do try to keep up with SV as
a good engineer needs to know both.

Regards,
Hans
www.ht-lab.com

 

W dniu środa, 10 stycznia 2018 15:17:32 UTC+1 użytkownik john napisał:

I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

========================> http://johntech.co.uk
========================

I use mainly VHDL (I often design complex data acquisition and processing system and havily use VHDL records to describe complex data structures)
I'm trying to use systemVerilog

BR,
Wojtek

 

[Lars Asplund]

VHDL + VUnit (https://vunit.github.io/index.html)

Regards,
Lars

 

[Lars Asplund]

VHDL + VUnit (https://vunit.github.io/index.html)

Regards,
Lars

 

[Espen Tallaksen]

VHDL for design.
VHDL + UVVM (Universal VHDL Verification Methodology, Open source) for verification
https://github.com/UVVM/UVVM_All

Using VHDL with a good testbench architecture and a good infrastructure library allows very efficient verification.
BTW: UVVM also comes with open source BFMs (Bus Functional Models) and VVCs (VHDL Verification Components) for interfaces like AIX4-lite, AXI4-stream, Avalon MM, UART, I2C, SPI.

 

[Tobias Baumann]

VHDL for RTL (primarily FPGAs but ASIC in the past). VHDL + OSVVM for testbenches.

Same here. Even when not using OSVVM, I use VHDL primarly for my
testbenches, sometimes with PSL when needed.