Halt synthesiser with an assert?

[Tricky]

Do any Vendors synthesisors actually take action on asserts?

I can see it being quite useful, so why dont they do it?

for example:

...
generic (
word_width : integer; --Only use a multiple of 8
);
...

function check_generics return boolean is
begin
assert ( (word_width rem 8 ) = 0 )
report "word width must be a multiple of 8"
severity failure;
end function check_generics;

constant GEN_CHECK : boolean := check_generics;
begin
...

This would work quite happily in simulation, but if you gave it to
someone else as fully specced and working, they may not want to write
their own testbench to make sure it works (Im sure some people
do ) . This would stop them compiling it out of spec.

 

[Jonathan Bromley]

On Tue, 18 Nov 2008 09:34:36 -0800 (PST), Tricky
<Trickyhead@gmail.com> wrote:

Do any Vendors synthesisors actually take action on asserts?

I can see it being quite useful, so why dont they do it?

They do... don't they? I use such asserts, usually to
check the legality of generic values, and expect synth
tools to spot them (I always use "failure" severity,
so I don't know what would happen with other levels).

Time to go away and try a few examples in several
different tools....

It is easy to imagine situations where an IP vendor
would need synthesis to check that their customer
is not attempting to use absurd values for generics.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Tricky]

On 18 Nov, 17:39, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Tue, 18 Nov 2008 09:34:36 -0800 (PST), Tricky

Trickyh...@gmail.com> wrote:
Do any Vendors synthesisors actually take action on asserts?

I can see it being quite useful, so why dont they do it?

They do... don't they?  I use such asserts, usually to
check the legality of generic values, and expect synth
tools to spot them (I always use "failure" severity,
so I don't know what would happen with other levels).

Time to go away and try a few examples in several
different tools....

It is easy to imagine situations where an IP vendor
would need synthesis to check that their customer
is not attempting to use absurd values for generics.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Whoops, I think I jumped the gun.

It seems to work fine in brand A, evening giving justs a warning.

I dont know where I got my idea from.

 

[Mike Treseler]

Tricky wrote:

Whoops, I think I jumped the gun.
It seems to work fine in brand A, even giving just a warning.
I dont know where I got my idea from.

I have found that inspiration always
waits on the event 'press_send'

 

[Mark McDougall]

Mike Treseler wrote:

I have found that inspiration always
waits on the event 'press_send'

ROTFL!!! Nicely put!

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[Peter]

Whoops, I think I jumped the gun.

It seems to work fine in brand A, evening giving justs a warning.

I dont know where I got my idea from.

Maybe I did something wrong, but it didnt work using Lattice ispLEVER
software with Synplify....

/Peter

 

[Peter]

On 19 Nov, 15:41, Peter <peter.hermans...@sts.saab.se> wrote:

Whoops, I think I jumped the gun.

It seems to work fine in brand A, evening giving justs a warning.

I dont know where I got my idea from.

Maybe I did something wrong, but it didnt work using Lattice ispLEVER
software with Synplify....

/Peter

From the Synplify manual:

Ignored VHDL Language Constructs:
The synthesis tool ignores the following constructs in your design. If
found,
the tool parses and ignores them and continues with the synthesis run.
• disconnect
• assert and report

Bad news...

The same result with Mentors "Precision Synthesis".

 

[HT-Lab]

"Peter" <peter.hermansson@sts.saab.se> wrote in message
news:1471f587-1099-46ef-bcf6-d854514b2df8@s9g2000prg.googlegroups.com...
On 19 Nov, 15:41, Peter <peter.hermans...@sts.saab.se> wrote:

Whoops, I think I jumped the gun.

It seems to work fine in brand A, evening giving justs a warning.

I dont know where I got my idea from.

Maybe I did something wrong, but it didnt work using Lattice ispLEVER
software with Synplify....

/Peter

From the Synplify manual:

Ignored VHDL Language Constructs:
The synthesis tool ignores the following constructs in your design. If
found,
the tool parses and ignores them and continues with the synthesis run.
• disconnect
• assert and report

Bad news...

The same result with Mentors "Precision Synthesis".

I just tried it out in Precision 2008a and it does evaluate the assertion,

entity cntgen is
GENERIC(CNTRESET : std_logic_vector(7 downto 0):="00000000");

assert ( CNTRESET = "10000000")
report "blablabla" severity failure;

# Info: [44522]: Root Module work.cntgen(rtl){generic map (CNTRESET(7 downto
0) => 00)}: Pre-processing...
# Warning: [45547]: "countergen_assert.vhd", line 24: Assertion Failed:
failure : blablabla

If you change the generic to "10000000" the warning goes away,

Hans
www.ht-lab.com

 

[Jonathan Bromley]

On Wed, 19 Nov 2008 07:14:23 -0800 (PST), Peter wrote:

From the Synplify manual:

Ignored VHDL Language Constructs:
The synthesis tool ignores the following constructs in your design. If
found,
the tool parses and ignores them and continues with the synthesis run.
• disconnect
• assert and report

Bad news...

The same result with Mentors "Precision Synthesis".

It is bad news, but in the case of Mentor Precision
(and, indeed, the older Mentor tool "Leonardo Spectrum")
you get a warning message; the docs are (slightly) wrong.

Synplify does indeed completely ignore the assertion
(even when used sensibly, as a concurrent assertion).
Synopsys DC likewise ignores it. Grrr. It's
inexcusable and silly; assertions over constants
should be processed by synth tools and failures
should be fatal failures.

Obviously the synth tool cannot give errors for
assertions that test things that can vary at runtime,
but assertions over generic and constant values
are an important technique and IMO it's outrageous
that they are not fully supported in synthesis.

I wonder if things will change when SystemVerilog
gains elaboration-time assertion constructs, in
the 2009 revision?

I haven't tried it in Quartus or ISE.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[KJ]

On Nov 19, 11:54 am, Jonathan Bromley
<jonathan.brom...@MYCOMPANY.com>

Synplify does indeed completely ignore the assertion
(even when used sensibly, as a concurrent assertion).
Synopsys DC likewise ignores it. Grrr. It's
inexcusable and silly; assertions over constants
should be processed by synth tools and failures
should be fatal failures.

Obviously the synth tool cannot give errors for
assertions that test things that can vary at runtime,
but assertions over generic and constant values
are an important technique and IMO it's outrageous
that they are not fully supported in synthesis.

I wonder if things will change when SystemVerilog
gains elaboration-time assertion constructs, in
the 2009 revision?

Wondering will not cause change, taking appropriate action might.

As I have often suggested in the past, the appropriate action here
would be to open a case with Synopsys regarding Synplify (and other
laggard synth tool suppliers) as a new feature request to support
evaluation of static assertions and have it return the appropriate
severity level to the tool so that synthesis stops on 'error' or
'fatal' as it should.

As ammo, use the fact that Quartus supports assertions and has for
quite some time and does just what I described.

My track record with Synplicity (i.e. before Synopsys) was spotty in
that sometimes they would fix the tool, sometimes they would disappear
into a black hole. So far with Synopsys I can say that they appear to
be taking the requests a bit more seriously, they have moved several
bugs/features from 'bug submitted' to 'fixed' to 'closed'.

Requesting VHDL-200x features is not the only thing that synthesis
tool suppliers need to be hammered on for requests, requesting VHDL-87
and VHDL-93 features is fair game too...if they want to lie back on
their statement that "we don't support such and such feature, it says
so in the manual or log file" fine, but such actions over time tend to
push designers to using other tools and cause lost revenue to the
supplier as it should.

I haven't tried it in Quartus or ISE.

I have with Quartus, it's worked for several years.

Kevin Jennings

 

[KJ]

From the Synplify manual:

Ignored VHDL Language Constructs:
The synthesis tool ignores the following constructs in your design. If
found,
the tool parses and ignores them and continues with the synthesis run.
• disconnect
• assert and report

Submit a feature suggestion to Synopsys then and tell them that the
competition (i.e. Quartus and Precision) supports assertions and so
should Synplify.

assert ( CNTRESET = "10000000")
report "blablabla" severity failure;

# Info: [44522]: Root Module work.cntgen(rtl){generic map (CNTRESET(7 downto
0) => 00)}: Pre-processing...
# Warning: [45547]: "countergen_assert.vhd", line 24: Assertion Failed:
failure : blablabla

If you change the generic to "10000000" the warning goes away,

Submit a bug report on Precision then for changing a 'failure'
assertion level into a 'warning'.

Kevin Jennings

 

[Tricky]

I haven't tried it in Quartus or ISE.

Works fine in Quartus 5.1 and 8.1. This is from assigning a constant
via a function (that checks generics), and the assert inside the
function. It works for either:

assert (good)
report "" severity failure;

or:

if (not good) then
report "" severity failure.

Warning and Note severities are also dealt with appropriatly.

 

[Jonathan Bromley]

On Wed, 19 Nov 2008 09:27:23 -0800 (PST), KJ wrote:

I wonder if things will change when SystemVerilog
gains elaboration-time assertion constructs, in
the 2009 revision?

Wondering will not cause change, taking appropriate action might.

My tongue was in my cheek; big-bucks tool vendors have
typically given much more mind-share to Verilog than VHDL.

As I have often suggested in the past, the appropriate action here
would be to open a case

Indeed. I'm amazed the design-IP community hasn't already
beaten the synth vendors' doors down about this.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Jonathan Bromley wrote:

I'm amazed the design-IP community hasn't already
beaten the synth vendors' doors down about this.

Most of that community uses
the "verilog subset" of vhdl.

-- Mike Treseler

 

[KJ]

On Nov 19, 1:44 pm, Mike Treseler <mtrese...@gmail.com> wrote:

Jonathan Bromley wrote:
I'm amazed the design-IP community hasn't already
beaten the synth vendors' doors down about this.

Most of that community uses
the "verilog subset" of vhdl.

Or they mostly use Quartus.

KJ

 

[HT-Lab]

assert ( CNTRESET = "10000000")
report "blablabla" severity failure;

# Info: [44522]: Root Module work.cntgen(rtl){generic map (CNTRESET(7
downto
0) => 00)}: Pre-processing...
# Warning: [45547]: "countergen_assert.vhd", line 24: Assertion Failed:
failure : blablabla

If you change the generic to "10000000" the warning goes away,

.
Submit a bug report on Precision then for changing a 'failure'
assertion level into a 'warning'.

Kevin Jennings

Done, logged with Mentor under SR:2198125211

Hans
www.ht-lab.com

 

[Dave]

On Nov 18, 12:34 pm, Tricky <Trickyh...@gmail.com> wrote:

Do any Vendors synthesisors actually take action on asserts?

I can see it being quite useful, so why dont they do it?

for example:

..
generic (
  word_width : integer; --Only use a multiple of 8
  );
..

function check_generics return boolean is
begin
  assert ( (word_width rem 8 ) = 0 )
    report "word width must be a multiple of 8"
      severity failure;
end function check_generics;

constant GEN_CHECK : boolean := check_generics;
begin
..

This would work quite happily in simulation, but if you gave it to
someone else as fully specced and working, they may not want to write
their own testbench to make sure it works (Im sure some people
do ) . This would stop them compiling it out of spec.

Xilinx XST 10.1 SP3 looks like it works, at least for concurrent
assert checking a generic value and reporting a failure.

Dave

 

[Sean Durkin]

Jonathan Bromley wrote:

Indeed. I'm amazed the design-IP community hasn't already
beaten the synth vendors' doors down about this.

FWIW, I recently contacted Mentor about this, since Precision only
issues warnings when an assertion with severity error or failure occurs.

They responded that some of their biggest customers explicitely wanted
that behaviour, since assertions should be used for simulation only and
some of their code would not synthesize anymore. I suppose it's similar
for other vendor's tools.

At least, for Precision there's an undocumented command-line switch that
enables it. Just so it propagates into all the search engines:

setup_design -var "rtl_extra_options=-allow_assert_error"

Mentor opened a DR to introduce this as an official "feature" in some
future release.

cu,
Sean

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