Ground Plane vs Power Plane

[bitrex]

On 6/16/19 8:52 PM, John Larkin wrote:

On Sun, 16 Jun 2019 18:49:00 -0400, bitrex <user@example.net> wrote:

On 6/16/19 6:45 PM, bitrex wrote:
On 6/16/19 5:18 PM, John Larkin wrote:
On Sun, 16 Jun 2019 10:37:12 -0700 (PDT), Fibo <panfilero@gmail.com
wrote:

On Sunday, June 16, 2019 at 1:15:53 AM UTC-5, bitrex wrote:
On 6/15/19 4:45 PM, Fibo wrote:
Hello,

I'm trying to layout a little board with a WiFi module (WL1835MOD),
a Beaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC
(AD9238)... they don't all fit on one side of the board, their
datasheets all want ground planes under them... if I put the ADC on
the bottom of the board and have a Power Plane under it, is that
close enough to having a ground plane under the part? or can a
ground pour under the IC take the place of a ground plane?

If not, then I guess a 6-layer stack up

- signal (top)
- gnd
- pwr
- gnd
- signal (bottom)

or is that overkill?

Much thank!


If you're talking about an ADC then you're implicitly talking about a
mixed-signal board. you're not mixing your analog and digital supplies,
are you?

There should be independent supplies for the analog and digital
sections. They should be isolated from each other on the board, too.
Many ADC mfgrs kindly put all the digital pins on one side of the IC
and
the analog pins on the other to help accomplish this

I do have an ADC on the bottom of the board, I will have split analog
and digital power planes, but just one solid ground... I have the
processor and wifi modules on top, and adc on bottom... I'm going to
do six layers.... I'm debating between these two stack ups:

1 - top
2 - gnd
3 - sig
4 - pwr
5 - gnd
6 - bottom

or

1 - top
2 - gnd
3 - sig
4 - sig
5 - pwr
6 - bottom

I feel like the first stack up may be better? There's also an SD card
on the bottom, and USB on top

Probably doesn't matter. Just avoid crosstalk on the sig-sig pair.
Well, avoid crosstalk everywhere!

We generally use just one ground plane, so as to have more routing and
sometimes power pour space.

L3 power close to L2 ground is probably better for *really* fast
stuff.  It minimizes power inductance and maximizes plane capacitance.

There are so many competing theories (and so much included nonsense)
about signal integrity precisely because most of the theories work.

The Saturn PCB Toolkit is good for calculating trace impedances,
especially for odd things like asymmetric microstrip, which is what
you have with plane-sig-sig-plane.



A six-layer board seems an awful big stack for three chips, where one is
a BGA SoC. The non-SoC Beaglebone with external RAM, etc. is 6 layers
it's a much more complicated board.

Shit you could probably do a budget-oriented PCIe video card in six
layers nowatimes.

(I have learned to wait until you finish discussing things with
yourself.)

This antiquated technology doesn't seem to support an "edit post"
feature reliably, an addendum is what's available.

I grew up with the ability to modify posts. I'm really spoiled, I know

The problem with BGAs is getting the traces out. You can get the two
outer rows of balls out on layer 1, but after that each row needs
another layer. Then you have ground and probably several power
supplies to pour into the array.

This was intended to be an 8 layer board, but it was taking so long to
route we went to 10.

https://www.dropbox.com/s/27rb966kjivbwr7/P5_Big_BGA.jpg?raw=1

That needs four layers to get ground and power into the chip.

The SoC in the OP's design is a somewhat more modest affair; the mfgr in
question is even kind enough to provide a reference on how to free them
all on a single layer. Luxurious of them, I know!

<http://octavosystems.com/octavosystems.com/wp-content/uploads/2017/05/Single-Layer-Body.png>

 

On Sun, 16 Jun 2019 19:54:59 -0700 (PDT), Rick C
<gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 9:07:39 PM UTC-4, k...@notreal.com wrote:
On Sun, 16 Jun 2019 13:44:16 -0700 (PDT), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 1:37:18 PM UTC-4, Fibo wrote:
On Sunday, June 16, 2019 at 1:15:53 AM UTC-5, bitrex wrote:
On 6/15/19 4:45 PM, Fibo wrote:
Hello,

I'm trying to layout a little board with a WiFi module (WL1835MOD), a Beaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC (AD9238)... they don't all fit on one side of the board, their datasheets all want ground planes under them... if I put the ADC on the bottom of the board and have a Power Plane under it, is that close enough to having a ground plane under the part? or can a ground pour under the IC take the place of a ground plane?

If not, then I guess a 6-layer stack up

- signal (top)
- gnd
- pwr
- gnd
- signal (bottom)

or is that overkill?

Much thank!


If you're talking about an ADC then you're implicitly talking about a
mixed-signal board. you're not mixing your analog and digital supplies,
are you?

There should be independent supplies for the analog and digital
sections. They should be isolated from each other on the board, too.
Many ADC mfgrs kindly put all the digital pins on one side of the IC and
the analog pins on the other to help accomplish this

I do have an ADC on the bottom of the board, I will have split analog and digital power planes, but just one solid ground... I have the processor and wifi modules on top, and adc on bottom... I'm going to do six layers.... I'm debating between these two stack ups:

1 - top
2 - gnd
3 - sig
4 - pwr
5 - gnd
6 - bottom

Good, though it uses an additional plane. The grounds have to be well
stitched, too.

or

1 - top
2 - gnd
3 - sig
4 - sig
5 - pwr
6 - bottom

This is good if there are a large number of high-speed traces. We did
this sort of stackup (a ground or power against all signals) when I
was at IBM.

I feel like the first stack up may be better? There's also an SD card on the bottom, and USB on top

USB is supposed to be impedance controlled. So that might work best on either of your stackups. I would prefer to use

1 - top
2 - sig
3 - gnd
4 - pwr
5 - sig
6 - bottom

The issue is the distance between the planes. They're not always
equidistant. I'd prefer this stackup but only if there is only
prepreg between 3&4.

What do you mean "they" are not always equidistant? If you mean the layer thicknesses that is for the designer to specify.

Sure but the optimum plane assignment can't be made independent of the
interplane distances. The above discussion means nothing without
knowing (or, better, specifying) the dielectric thicknesses.

 

[Rick C]

On Sunday, June 16, 2019 at 9:07:39 PM UTC-4, k...@notreal.com wrote:

On Sun, 16 Jun 2019 13:44:16 -0700 (PDT), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 1:37:18 PM UTC-4, Fibo wrote:
On Sunday, June 16, 2019 at 1:15:53 AM UTC-5, bitrex wrote:
On 6/15/19 4:45 PM, Fibo wrote:
Hello,

I'm trying to layout a little board with a WiFi module (WL1835MOD), a Beaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC (AD9238)... they don't all fit on one side of the board, their datasheets all want ground planes under them... if I put the ADC on the bottom of the board and have a Power Plane under it, is that close enough to having a ground plane under the part? or can a ground pour under the IC take the place of a ground plane?

If not, then I guess a 6-layer stack up

- signal (top)
- gnd
- pwr
- gnd
- signal (bottom)

or is that overkill?

Much thank!


If you're talking about an ADC then you're implicitly talking about a
mixed-signal board. you're not mixing your analog and digital supplies,
are you?

There should be independent supplies for the analog and digital
sections. They should be isolated from each other on the board, too.
Many ADC mfgrs kindly put all the digital pins on one side of the IC and
the analog pins on the other to help accomplish this

I do have an ADC on the bottom of the board, I will have split analog and digital power planes, but just one solid ground... I have the processor and wifi modules on top, and adc on bottom... I'm going to do six layers..... I'm debating between these two stack ups:

1 - top
2 - gnd
3 - sig
4 - pwr
5 - gnd
6 - bottom

Good, though it uses an additional plane. The grounds have to be well
stitched, too.

or

1 - top
2 - gnd
3 - sig
4 - sig
5 - pwr
6 - bottom

This is good if there are a large number of high-speed traces. We did
this sort of stackup (a ground or power against all signals) when I
was at IBM.

I feel like the first stack up may be better? There's also an SD card on the bottom, and USB on top

USB is supposed to be impedance controlled. So that might work best on either of your stackups. I would prefer to use

1 - top
2 - sig
3 - gnd
4 - pwr
5 - sig
6 - bottom

The issue is the distance between the planes. They're not always
equidistant. I'd prefer this stackup but only if there is only
prepreg between 3&4.

What do you mean "they" are not always equidistant? If you mean the layer thicknesses that is for the designer to specify.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Sunday, June 16, 2019 at 6:45:18 PM UTC-4, bitrex wrote:

On 6/16/19 5:18 PM, John Larkin wrote:
On Sun, 16 Jun 2019 10:37:12 -0700 (PDT), Fibo <panfilero@gmail.com
wrote:

On Sunday, June 16, 2019 at 1:15:53 AM UTC-5, bitrex wrote:
On 6/15/19 4:45 PM, Fibo wrote:
Hello,

I'm trying to layout a little board with a WiFi module (WL1835MOD), a Beaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC (AD9238)... they don't all fit on one side of the board, their datasheets all want ground planes under them... if I put the ADC on the bottom of the board and have a Power Plane under it, is that close enough to having a ground plane under the part? or can a ground pour under the IC take the place of a ground plane?

If not, then I guess a 6-layer stack up

- signal (top)
- gnd
- pwr
- gnd
- signal (bottom)

or is that overkill?

Much thank!


If you're talking about an ADC then you're implicitly talking about a
mixed-signal board. you're not mixing your analog and digital supplies,
are you?

There should be independent supplies for the analog and digital
sections. They should be isolated from each other on the board, too.
Many ADC mfgrs kindly put all the digital pins on one side of the IC and
the analog pins on the other to help accomplish this

I do have an ADC on the bottom of the board, I will have split analog and digital power planes, but just one solid ground... I have the processor and wifi modules on top, and adc on bottom... I'm going to do six layers..... I'm debating between these two stack ups:

1 - top
2 - gnd
3 - sig
4 - pwr
5 - gnd
6 - bottom

or

1 - top
2 - gnd
3 - sig
4 - sig
5 - pwr
6 - bottom

I feel like the first stack up may be better? There's also an SD card on the bottom, and USB on top

Probably doesn't matter. Just avoid crosstalk on the sig-sig pair.
Well, avoid crosstalk everywhere!

We generally use just one ground plane, so as to have more routing and
sometimes power pour space.

L3 power close to L2 ground is probably better for *really* fast
stuff. It minimizes power inductance and maximizes plane capacitance.

There are so many competing theories (and so much included nonsense)
about signal integrity precisely because most of the theories work.

The Saturn PCB Toolkit is good for calculating trace impedances,
especially for odd things like asymmetric microstrip, which is what
you have with plane-sig-sig-plane.



A six-layer board seems an awful big stack for three chips, where one is
a BGA SoC. The non-SoC Beaglebone with external RAM, etc. is 6 layers
it's a much more complicated board.

If you want full power and ground planes, depending on the specific BGA, it can be hard to route all the signals on a 4 layer board.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[John Larkin]

On Sun, 16 Jun 2019 23:07:53 -0400, bitrex <user@example.net> wrote:

On 6/16/19 8:52 PM, John Larkin wrote:
On Sun, 16 Jun 2019 18:49:00 -0400, bitrex <user@example.net> wrote:

On 6/16/19 6:45 PM, bitrex wrote:
On 6/16/19 5:18 PM, John Larkin wrote:
On Sun, 16 Jun 2019 10:37:12 -0700 (PDT), Fibo <panfilero@gmail.com
wrote:

On Sunday, June 16, 2019 at 1:15:53 AM UTC-5, bitrex wrote:
On 6/15/19 4:45 PM, Fibo wrote:
Hello,

I'm trying to layout a little board with a WiFi module (WL1835MOD),
a Beaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC
(AD9238)... they don't all fit on one side of the board, their
datasheets all want ground planes under them... if I put the ADC on
the bottom of the board and have a Power Plane under it, is that
close enough to having a ground plane under the part? or can a
ground pour under the IC take the place of a ground plane?

If not, then I guess a 6-layer stack up

- signal (top)
- gnd
- pwr
- gnd
- signal (bottom)

or is that overkill?

Much thank!


If you're talking about an ADC then you're implicitly talking about a
mixed-signal board. you're not mixing your analog and digital supplies,
are you?

There should be independent supplies for the analog and digital
sections. They should be isolated from each other on the board, too.
Many ADC mfgrs kindly put all the digital pins on one side of the IC
and
the analog pins on the other to help accomplish this

I do have an ADC on the bottom of the board, I will have split analog
and digital power planes, but just one solid ground... I have the
processor and wifi modules on top, and adc on bottom... I'm going to
do six layers.... I'm debating between these two stack ups:

1 - top
2 - gnd
3 - sig
4 - pwr
5 - gnd
6 - bottom

or

1 - top
2 - gnd
3 - sig
4 - sig
5 - pwr
6 - bottom

I feel like the first stack up may be better? There's also an SD card
on the bottom, and USB on top

Probably doesn't matter. Just avoid crosstalk on the sig-sig pair.
Well, avoid crosstalk everywhere!

We generally use just one ground plane, so as to have more routing and
sometimes power pour space.

L3 power close to L2 ground is probably better for *really* fast
stuff.  It minimizes power inductance and maximizes plane capacitance.

There are so many competing theories (and so much included nonsense)
about signal integrity precisely because most of the theories work.

The Saturn PCB Toolkit is good for calculating trace impedances,
especially for odd things like asymmetric microstrip, which is what
you have with plane-sig-sig-plane.



A six-layer board seems an awful big stack for three chips, where one is
a BGA SoC. The non-SoC Beaglebone with external RAM, etc. is 6 layers
it's a much more complicated board.

Shit you could probably do a budget-oriented PCIe video card in six
layers nowatimes.

(I have learned to wait until you finish discussing things with
yourself.)

This antiquated technology doesn't seem to support an "edit post"
feature reliably, an addendum is what's available.

I grew up with the ability to modify posts. I'm really spoiled, I know

The problem with BGAs is getting the traces out. You can get the two
outer rows of balls out on layer 1, but after that each row needs
another layer. Then you have ground and probably several power
supplies to pour into the array.

This was intended to be an 8 layer board, but it was taking so long to
route we went to 10.

https://www.dropbox.com/s/27rb966kjivbwr7/P5_Big_BGA.jpg?raw=1

That needs four layers to get ground and power into the chip.


The SoC in the OP's design is a somewhat more modest affair; the mfgr in
question is even kind enough to provide a reference on how to free them
all on a single layer. Luxurious of them, I know!

http://octavosystems.com/octavosystems.com/wp-content/uploads/2017/05/Single-Layer-Body.png

What's the trace width? They are running two traces beween balls.

Only three balls deep.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[John Larkin]

On Sun, 16 Jun 2019 20:59:38 -0400, krw@notreal.com wrote:

On Sat, 15 Jun 2019 22:10:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:


Big power planes have a useful amount of fast capacitance. But what's
really great about power planes or pours is their super low
inductance, compared to a trace. A plane is a great way to connect
several bypass caps to several parts. Fast current spikes spread out
in all directions.

If you TDR a power plane against ground, it looks like an almost
perfect capacitor. If you then add bypass caps anywhere on the plane,
it looks like a bigger capacitor.

https://www.dropbox.com/s/wkiehn6iowq3emf/TDR_3Vplane.JPG?raw=1

How much lumped capacitance is on the board? ...or is this all the
ground plane? It would be good to see the same trace with and without
a lumped capacitor at a significant distance (e.g. 5ns) from the
injection point.

That was a bare board, no caps installed. The SMA connector scopes the
3.3 volt power plane against ground. You can figure out the
capacitance from the charging curve. In my experience, adding any
bypass cap anywhere on the plane just makes it look like a bigger
capacitance. With good ground and power planes, it doesn't much matter
where you put the bypass caps. The parasitic inductance of the cap and
vias don't seem to matter either; the plane itself is the high
frequency bypass.

It's a "solder sample" board, which is why it has a hole punched in
it, to make it unusable.

I've been trying to get management to buy a TDR but everyone else is
arguing that a network analyzer and software is a better use of the
limited cash. They won't buy eBay stuff. Go figure.

I have the PCB for a cheap TDR, but I haven't had time to make it
work.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Bill Sloman]

On Saturday, June 15, 2019 at 11:01:27 PM UTC+2, Rick C wrote:

On Saturday, June 15, 2019 at 4:45:57 PM UTC-4, Fibo wrote:
Hello,

I'm trying to layout a little board with a WiFi module (WL1835MOD), a Beaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC (AD9238)... they don't all fit on one side of the board, their datasheets all want ground planes under them... if I put the ADC on the bottom of the board and have a Power Plane under it, is that close enough to having a ground plane under the part? or can a ground pour under the IC take the place of a ground plane?

If not, then I guess a 6-layer stack up

- signal (top)
- gnd
- pwr
- gnd
- signal (bottom)

or is that overkill?

Much thank!

If they are adequately decoupled (why do they call it decoupling when the two planes are being coupled together?) the power plane is just as good as a ground. But that's only true if you do not have significant currents causing local voltage variations in the power plane.

All the current flowing through the power plane has to flow back out again through the ground plane (or another power plane).

Kirchoff's Law means that you have to think about current loops, not one-way current flows.

> Typically an ADC will have a separate power/ground plane from digital circuitry connected at just one point to prevent digitally induced currents from messing with the ADC.

It's better though of in terms of controlling the path followed by particular current loops. There's rarely just one.

> Your stackup is actually 5 layers, but you have the idea. You can do S1 G1 P1 P2 G2 S2

Printed circuit manufacturers don't seem to offer 5-layer boards.

--
Bill Sloman, Sydney

 

On Sun, 16 Jun 2019 20:11:51 -0700 (PDT), Rick C
<gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 10:59:57 PM UTC-4, k...@notreal.com wrote:

Sure but the optimum plane assignment can't be made independent of the
interplane distances. The above discussion means nothing without
knowing (or, better, specifying) the dielectric thicknesses.

I can set those distances to whatever works for the stackup I choose. What you are you trying to say? You don't need to use the same thicknesses for each stackup. This is not a test question with arbitrary constraints.

Dumbass, I'm saying that you didn't make any sense when you proposed
the "better" stack up without specifying interplane spacing at the
same time. It matters.

 

[Rick C]

On Tuesday, June 18, 2019 at 10:29:50 PM UTC-4, k...@notreal.com wrote:

On Sun, 16 Jun 2019 20:11:51 -0700 (PDT), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 10:59:57 PM UTC-4, k...@notreal.com wrote:

Sure but the optimum plane assignment can't be made independent of the
interplane distances. The above discussion means nothing without
knowing (or, better, specifying) the dielectric thicknesses.

I can set those distances to whatever works for the stackup I choose. What you are you trying to say? You don't need to use the same thicknesses for each stackup. This is not a test question with arbitrary constraints.

Dumbass, I'm saying that you didn't make any sense when you proposed
the "better" stack up without specifying interplane spacing at the
same time. It matters.

It matters in what way? Setting the interplane spacing depends on the many unspecified requirements. The interplane capacitance can be maximized by making the spacing as thin as possible. But there is no reason to sacrifice other unspecified design aspects like controlled impedances unless you can't meet the unspecified PDS requirements otherwise.

So give me the requirements and I'll give you the plane spacings... dumbass..

Why do you have to call people names just because you don't understand what they are saying?

Are you only twelve?

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

 

On Tue, 18 Jun 2019 19:47:20 -0700 (PDT), Rick C
<gnuarm.deletethisbit@gmail.com> wrote:

On Tuesday, June 18, 2019 at 10:29:50 PM UTC-4, k...@notreal.com wrote:
On Sun, 16 Jun 2019 20:11:51 -0700 (PDT), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 10:59:57 PM UTC-4, k...@notreal.com wrote:

Sure but the optimum plane assignment can't be made independent of the
interplane distances. The above discussion means nothing without
knowing (or, better, specifying) the dielectric thicknesses.

I can set those distances to whatever works for the stackup I choose. What you are you trying to say? You don't need to use the same thicknesses for each stackup. This is not a test question with arbitrary constraints.

Dumbass, I'm saying that you didn't make any sense when you proposed
the "better" stack up without specifying interplane spacing at the
same time. It matters.

It matters in what way? Setting the interplane spacing depends on the many unspecified requirements. The interplane capacitance can be maximized by making the spacing as thin as possible. But there is no reason to sacrifice other unspecified design aspects like controlled impedances unless you can't meet the unspecified PDS requirements otherwise.

You're obviously too stupid to understand the basics.

So give me the requirements and I'll give you the plane spacings... dumbass.

Why do you have to call people names just because you don't understand what they are saying?

Are you only twelve?

Only five and a half times over.

 

On Sun, 16 Jun 2019 20:59:49 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Sun, 16 Jun 2019 20:59:38 -0400, krw@notreal.com wrote:

On Sat, 15 Jun 2019 22:10:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:


Big power planes have a useful amount of fast capacitance. But what's
really great about power planes or pours is their super low
inductance, compared to a trace. A plane is a great way to connect
several bypass caps to several parts. Fast current spikes spread out
in all directions.

If you TDR a power plane against ground, it looks like an almost
perfect capacitor. If you then add bypass caps anywhere on the plane,
it looks like a bigger capacitor.

https://www.dropbox.com/s/wkiehn6iowq3emf/TDR_3Vplane.JPG?raw=1

How much lumped capacitance is on the board? ...or is this all the
ground plane? It would be good to see the same trace with and without
a lumped capacitor at a significant distance (e.g. 5ns) from the
injection point.

That was a bare board, no caps installed. The SMA connector scopes the
3.3 volt power plane against ground. You can figure out the
capacitance from the charging curve. In my experience, adding any
bypass cap anywhere on the plane just makes it look like a bigger
capacitance. With good ground and power planes, it doesn't much matter
where you put the bypass caps. The parasitic inductance of the cap and
vias don't seem to matter either; the plane itself is the high
frequency bypass.

Sure but I wanted to see evidence that the location of the cap didn't
matter. I'd do it but we don't have a TDR, or boards with a nice SMA
connected neatly to the planes.

It's a "solder sample" board, which is why it has a hole punched in
it, to make it unusable.

Understood. You could still use it to demonstrate the issue.

I've been trying to get management to buy a TDR but everyone else is
arguing that a network analyzer and software is a better use of the
limited cash. They won't buy eBay stuff. Go figure.

I have the PCB for a cheap TDR, but I haven't had time to make it
work.

I want a rather good one. An 1180x/SD24 should be good enough. A
network analyzer seems like gilding the Lilly and perhaps more
complicated than its worth.

 

[John Larkin]

On Wed, 19 Jun 2019 22:21:21 -0400, krw@notreal.com wrote:

On Sun, 16 Jun 2019 20:59:49 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 16 Jun 2019 20:59:38 -0400, krw@notreal.com wrote:

On Sat, 15 Jun 2019 22:10:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:


Big power planes have a useful amount of fast capacitance. But what's
really great about power planes or pours is their super low
inductance, compared to a trace. A plane is a great way to connect
several bypass caps to several parts. Fast current spikes spread out
in all directions.

If you TDR a power plane against ground, it looks like an almost
perfect capacitor. If you then add bypass caps anywhere on the plane,
it looks like a bigger capacitor.

https://www.dropbox.com/s/wkiehn6iowq3emf/TDR_3Vplane.JPG?raw=1

How much lumped capacitance is on the board? ...or is this all the
ground plane? It would be good to see the same trace with and without
a lumped capacitor at a significant distance (e.g. 5ns) from the
injection point.

That was a bare board, no caps installed. The SMA connector scopes the
3.3 volt power plane against ground. You can figure out the
capacitance from the charging curve. In my experience, adding any
bypass cap anywhere on the plane just makes it look like a bigger
capacitance. With good ground and power planes, it doesn't much matter
where you put the bypass caps. The parasitic inductance of the cap and
vias don't seem to matter either; the plane itself is the high
frequency bypass.

Sure but I wanted to see evidence that the location of the cap didn't
matter. I'd do it but we don't have a TDR, or boards with a nice SMA
connected neatly to the planes.

It's a "solder sample" board, which is why it has a hole punched in
it, to make it unusable.

Understood. You could still use it to demonstrate the issue.

Trust me.

I've been trying to get management to buy a TDR but everyone else is
arguing that a network analyzer and software is a better use of the
limited cash. They won't buy eBay stuff. Go figure.

I have the PCB for a cheap TDR, but I haven't had time to make it
work.

I want a rather good one. An 1180x/SD24 should be good enough. A
network analyzer seems like gilding the Lilly and perhaps more
complicated than its worth.

I have an 11802 on my bench, and a bunch of SD24s and other heads. The
SD24 can do TDR and TDT simultaneously. You can also use one TDR
channel as a trigger out to things, and snoop the results on the
other.

SD14 is cool too, a dual channel 3 GHz HiZ probe. Something like 0.25
pF at the probe tips.

A VNA can be used to fake TDR, with some FFT math or something. But
response doesn't go down to DC.


--

John Larkin Highland Technology, Inc

lunatic fringe electronics

 

[Bill Sloman]

On Thursday, June 20, 2019 at 4:22:57 AM UTC+2, k...@notreal.com wrote:

On Tue, 18 Jun 2019 19:47:20 -0700 (PDT), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Tuesday, June 18, 2019 at 10:29:50 PM UTC-4, k...@notreal.com wrote:
On Sun, 16 Jun 2019 20:11:51 -0700 (PDT), Rick C
gnuarm.deletethisbit@gmail.com> wrote:

On Sunday, June 16, 2019 at 10:59:57 PM UTC-4, k...@notreal.com wrote:

Sure but the optimum plane assignment can't be made independent of the
interplane distances. The above discussion means nothing without
knowing (or, better, specifying) the dielectric thicknesses.

I can set those distances to whatever works for the stackup I choose. What you are you trying to say? You don't need to use the same thicknesses for each stackup. This is not a test question with arbitrary constraints.

Dumbass, I'm saying that you didn't make any sense when you proposed
the "better" stack up without specifying interplane spacing at the
same time. It matters.

It matters in what way? Setting the interplane spacing depends on the many unspecified requirements. The interplane capacitance can be maximized by making the spacing as thin as possible. But there is no reason to sacrifice other unspecified design aspects like controlled impedances unless you can't meet the unspecified PDS requirements otherwise.

You're obviously too stupid to understand the basics.

But krw is much too stupid to illustate where Rick C has "failed to understand the basics", and rather too stupid to understand that what Rick C did post didn't illustrate any such failure.

So give me the requirements and I'll give you the plane spacings... dumbass.

Why do you have to call people names just because you don't understand what they are saying?

Are you only twelve?

Only five and a half times over.

Which is to say that krw is well into his second childhood and going backwards.

--
Bill Sloman, Sydney

 

On Wed, 19 Jun 2019 20:31:45 -0700, John Larkin
<jjlarkin@highlandtechnology.com> wrote:

On Wed, 19 Jun 2019 22:21:21 -0400, krw@notreal.com wrote:

On Sun, 16 Jun 2019 20:59:49 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 16 Jun 2019 20:59:38 -0400, krw@notreal.com wrote:

On Sat, 15 Jun 2019 22:10:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:


Big power planes have a useful amount of fast capacitance. But what's
really great about power planes or pours is their super low
inductance, compared to a trace. A plane is a great way to connect
several bypass caps to several parts. Fast current spikes spread out
in all directions.

If you TDR a power plane against ground, it looks like an almost
perfect capacitor. If you then add bypass caps anywhere on the plane,
it looks like a bigger capacitor.

https://www.dropbox.com/s/wkiehn6iowq3emf/TDR_3Vplane.JPG?raw=1

How much lumped capacitance is on the board? ...or is this all the
ground plane? It would be good to see the same trace with and without
a lumped capacitor at a significant distance (e.g. 5ns) from the
injection point.

That was a bare board, no caps installed. The SMA connector scopes the
3.3 volt power plane against ground. You can figure out the
capacitance from the charging curve. In my experience, adding any
bypass cap anywhere on the plane just makes it look like a bigger
capacitance. With good ground and power planes, it doesn't much matter
where you put the bypass caps. The parasitic inductance of the cap and
vias don't seem to matter either; the plane itself is the high
frequency bypass.

Sure but I wanted to see evidence that the location of the cap didn't
matter. I'd do it but we don't have a TDR, or boards with a nice SMA
connected neatly to the planes.

It's a "solder sample" board, which is why it has a hole punched in
it, to make it unusable.

Understood. You could still use it to demonstrate the issue.

Trust me.

I believe you but my cow-orkers don't know what a nice guy you are.

I've been trying to get management to buy a TDR but everyone else is
arguing that a network analyzer and software is a better use of the
limited cash. They won't buy eBay stuff. Go figure.

I have the PCB for a cheap TDR, but I haven't had time to make it
work.

I want a rather good one. An 1180x/SD24 should be good enough. A
network analyzer seems like gilding the Lilly and perhaps more
complicated than its worth.

I have an 11802 on my bench, and a bunch of SD24s and other heads. The
SD24 can do TDR and TDT simultaneously. You can also use one TDR
channel as a trigger out to things, and snoop the results on the
other.

SD14 is cool too, a dual channel 3 GHz HiZ probe. Something like 0.25
pF at the probe tips.

A VNA can be used to fake TDR, with some FFT math or something. But
response doesn't go down to DC.

At a *much* higher cost. Not to mention complexity.

 

[John Larkin]

On Thu, 20 Jun 2019 22:30:24 -0400, krw@notreal.com wrote:

On Wed, 19 Jun 2019 20:31:45 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Wed, 19 Jun 2019 22:21:21 -0400, krw@notreal.com wrote:

On Sun, 16 Jun 2019 20:59:49 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:

On Sun, 16 Jun 2019 20:59:38 -0400, krw@notreal.com wrote:

On Sat, 15 Jun 2019 22:10:55 -0700, John Larkin
jjlarkin@highlandtechnology.com> wrote:


Big power planes have a useful amount of fast capacitance. But what's
really great about power planes or pours is their super low
inductance, compared to a trace. A plane is a great way to connect
several bypass caps to several parts. Fast current spikes spread out
in all directions.

If you TDR a power plane against ground, it looks like an almost
perfect capacitor. If you then add bypass caps anywhere on the plane,
it looks like a bigger capacitor.

https://www.dropbox.com/s/wkiehn6iowq3emf/TDR_3Vplane.JPG?raw=1

How much lumped capacitance is on the board? ...or is this all the
ground plane? It would be good to see the same trace with and without
a lumped capacitor at a significant distance (e.g. 5ns) from the
injection point.

That was a bare board, no caps installed. The SMA connector scopes the
3.3 volt power plane against ground. You can figure out the
capacitance from the charging curve. In my experience, adding any
bypass cap anywhere on the plane just makes it look like a bigger
capacitance. With good ground and power planes, it doesn't much matter
where you put the bypass caps. The parasitic inductance of the cap and
vias don't seem to matter either; the plane itself is the high
frequency bypass.

Sure but I wanted to see evidence that the location of the cap didn't
matter. I'd do it but we don't have a TDR, or boards with a nice SMA
connected neatly to the planes.

It's a "solder sample" board, which is why it has a hole punched in
it, to make it unusable.

Understood. You could still use it to demonstrate the issue.

Trust me.

I believe you but my cow-orkers don't know what a nice guy you are.


I've been trying to get management to buy a TDR but everyone else is
arguing that a network analyzer and software is a better use of the
limited cash. They won't buy eBay stuff. Go figure.

I have the PCB for a cheap TDR, but I haven't had time to make it
work.

I want a rather good one. An 1180x/SD24 should be good enough. A
network analyzer seems like gilding the Lilly and perhaps more
complicated than its worth.

I have an 11802 on my bench, and a bunch of SD24s and other heads. The
SD24 can do TDR and TDT simultaneously. You can also use one TDR
channel as a trigger out to things, and snoop the results on the
other.

SD14 is cool too, a dual channel 3 GHz HiZ probe. Something like 0.25
pF at the probe tips.

A VNA can be used to fake TDR, with some FFT math or something. But
response doesn't go down to DC.

At a *much* higher cost. Not to mention complexity.

I just sheared up my PCBWAY proto board, and I'm evaluating some
microwave-grade edge-launch SMA connectors. This boardlet has one
inexpensive Amphenol connector and one super-cheap Mueller.

https://www.dropbox.com/s/kgjk1o5clmef7zs/DSC03676.JPG?raw=1

https://www.dropbox.com/s/c1cx47wdjq000gj/DSC03677.JPG?raw=1

They both look pretty good, with small inductive bumps. Looks like I
nailed the 50 ohm CPW impedance pretty close, with the Saturn
software.

Maybe the inductive bumps are actually my necked-down trace. I can fix
that.

The first cursor dot in on the semi-hardline and the second is midway
along the trace.

I've got some more connectors to try, and some other layout
variations. I love TDR.

Maybe you can get an 11801 from a big-name broker.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com