Gray counter

[Guffi]

ast pisze:

Hi,

Do you know how to design a gray counter in VHDL ?

Better without a lookup table

The difficulty is to find a mathematical relation between the next state
and the current state.

thx
I think it was easy....

I think there was a mathematical solution using XOR gates
I'll try to find it and I'll write

 

[Guffi]

Guffi pisze:

ast pisze:
Hi,

Do you know how to design a gray counter in VHDL ?

Better without a lookup table

The difficulty is to find a mathematical relation between the next state
and the current state.

thx
I think it was easy....
I think there was a mathematical solution using XOR gates
I'll try to find it and I'll write

I wrote it some time ago
Hmm... I haven't checked it but i think it change binary to grey number
- if I remember correctly




entity nbit_koder is
generic (N: integer :=4);
port(A : in std_logic_vector(n-1 downto 0);
--B : in std_logic_vector(n-1 downto 0);
C : out std_logic_vector(n-1 downto 0));
end nbit_koder;




architecture arch_nbit_koder of nbit_koder is



component xor_gate
port (A,B: in std_logic;
C: out std_logic
);
end component;

signal tmp:std_logic_vector(n-1 downto 0);

begin

G: for I in 0 to (n-2) generate
GG: xor_gate port map ( A(i), A(i+1), C(i) );
end generate;

c(n-1)<=a(n-1);
end arch_nbit_koder;




library IEEE;
use ieee.std_logic_1164.all;

entity xor_gate is
port (A,B: in std_logic;
C: out std_logic
);

end xor_gate;

architecture arch_xor_gate of xor_gate is
begin
c<=a xor b;

end arch_xor_gate;