R
Rob Doyle
Guest
Sorry if this is a stupid question...
I have a simple tristate bus simulation that I can't make work with
GHDL. Attached.
It generates the following error:
error: invalid memory access (dangling accesses or stack size too small)
error: simulation failed
I've tried increasing the stack size but it still fails.
It seems to work with the Xilinx Webpack....
Any clues?
$ ghdl --version
GHDL 0.29.1 (20100301) [Sokcho edition]
Compiled with GNAT Version: GPL 2009 (20090519)
mcode code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2010 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There
is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE.
Rob.
------------ begin test_asdf.vhd ---------------
library ieee;
use ieee.std_logic_1164.all;
entity test_asdf is
end test_asdf;
architecture behav of test_asdf is
signal clk : std_logic := '0';
signal rst : std_logic;
signal data : std_logic;
signal dir : std_logic;
begin
uut : entity work.asdf (rtl) port map (
clk => clk,
rst => rst,
data => data,
dir => dir
);
process
begin
wait for 10 ns;
clk <= not(clk);
end process;
rst <= '1', '0' after 80 ns;
data <= '0' when dir = '0' else 'Z';
end behav;
-------------- end test_asdf.vhd --------
------------- start asdf.vhd --------------
library ieee;
use ieee.std_logic_1164.all;
entity asdf is port (
clk : in std_logic;
rst : in std_logic;
data : inout std_logic;
dir : out std_logic);
end asdf;
architecture rtl of asdf is
signal toggle : std_logic;
begin
process(clk, rst)
begin
if rst = '1' then
toggle <= '0';
elsif rising_edge(clk) then
toggle <= not(toggle);
end if;
end process;
data <= '1' when toggle = '1' else 'Z';
dir <= toggle;
end rtl;
-------------- end asdf.vhd -----------------
I have a simple tristate bus simulation that I can't make work with
GHDL. Attached.
It generates the following error:
error: invalid memory access (dangling accesses or stack size too small)
error: simulation failed
I've tried increasing the stack size but it still fails.
It seems to work with the Xilinx Webpack....
Any clues?
$ ghdl --version
GHDL 0.29.1 (20100301) [Sokcho edition]
Compiled with GNAT Version: GPL 2009 (20090519)
mcode code generator
Written by Tristan Gingold.
Copyright (C) 2003 - 2010 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License. There
is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE.
Rob.
------------ begin test_asdf.vhd ---------------
library ieee;
use ieee.std_logic_1164.all;
entity test_asdf is
end test_asdf;
architecture behav of test_asdf is
signal clk : std_logic := '0';
signal rst : std_logic;
signal data : std_logic;
signal dir : std_logic;
begin
uut : entity work.asdf (rtl) port map (
clk => clk,
rst => rst,
data => data,
dir => dir
);
process
begin
wait for 10 ns;
clk <= not(clk);
end process;
rst <= '1', '0' after 80 ns;
data <= '0' when dir = '0' else 'Z';
end behav;
-------------- end test_asdf.vhd --------
------------- start asdf.vhd --------------
library ieee;
use ieee.std_logic_1164.all;
entity asdf is port (
clk : in std_logic;
rst : in std_logic;
data : inout std_logic;
dir : out std_logic);
end asdf;
architecture rtl of asdf is
signal toggle : std_logic;
begin
process(clk, rst)
begin
if rst = '1' then
toggle <= '0';
elsif rising_edge(clk) then
toggle <= not(toggle);
end if;
end process;
data <= '1' when toggle = '1' else 'Z';
dir <= toggle;
end rtl;
-------------- end asdf.vhd -----------------