Generics in VHDL - number of components

[pbartosz]

I have an entity that is generic. For generic value N I'd like there
were N the same components (with single input signal) connected to
demultiplexer with N output signals. Is this doable (especially number
of components dependent of generic value)? Sample code, please.

 

[JB]

On 9 mar, 13:40, pbartosz <bartosz...@gmail.com> wrote:

I have an entity that is generic. For generic value N I'd like there
were N the same components (with single input signal) connected to
demultiplexer with N output signals. Is this doable (especially number
of components dependent of generic value)? Sample code, please.

Yes it is doable, a generate loop can instantiate your N components.

 

[hhanff]

On Mar 9, 3:00 pm, JB <jb.dubois....@gmail.com> wrote:

On 9 mar, 13:40, pbartosz <bartosz...@gmail.com> wrote:

I have an entity that is generic. For generic value N I'd like there
were N the same components (with single input signal) connected to
demultiplexer with N output signals. Is this doable (especially number
of components dependent of generic value)? Sample code, please.

Yes it is doable, a generate loop can instantiate your N components.

E.g.:

gen_ramb16_s1_s36 : for i in 0 to NUMBER_OF_RAMS_REQUIRED_C - 1
generate
RAMB16_S9_INSTANCE_NAME : RAMB16_S9
-- synthesis translate_off
generic map (
INIT => bit_value,
SRVAL => bit_value,
write_mode => user_WRITE_MODE,
-- [...]
INITP_07 => vector_value)
-- synopsys translate_on
port map (
DO => DO_RAM(i),
DOP => open,
ADDR => ADDR_RAM,
CLK => tcm8230md_sys_clk,
DI => tcm8239md_dout_s,
DIP => (others => '0'),
EN => '1', -- !!!
SSR => '0',
WE => WE_RAM(i));
end generate;