Generating PWM signals for testing ?

[asparnique]

Hi,

I was wondering if there is a way to generate PWM signals for testing
verilog code ? More so if there is a way to use as test signals, digitized
PWM signals as input signals for testing/simulating verilog code, such as
using a data file which represents a real PWM signal for instance ??

Cheers,
M

 

[Jonathan Bromley]

On Wed, 30 Dec 2009 19:22:07 +0100, "asparnique" wrote:

I was wondering if there is a way to generate PWM signals for testing
verilog code ?

Sure.

More so if there is a way to use as test signals, digitized
PWM signals as input signals for testing/simulating verilog code, such as
using a data file which represents a real PWM signal for instance ??

This is exactly the sort of thing you would expect to find
in a "test bench" - an additional (possibly quite large) piece of
Verilog code that simulates the behaviour of external signals that
provide inputs to your design under test (DUT), and checks that
the DUT's outputs have appropriate values at all times.

As an example, here's a little piece of Verilog that creates
a PWM signal (n/256) under control of a system clock. You
could use it as part of a testbench. Other parts of the
testbench would create the clock signal, and manipulate the
PwmValue variable to control what this generator does.
You could then connect PwmSignal to an input of your DUT.

// assume signal "clock" exists already in the testbench

integer PwmValue; // keep this in the range 0..256
reg PwmSignal; // this is the generated PWM test signal

initial begin : PwmGeneratorBlock
reg [7:0] counter;
PwmValue = 0; // because integers initialize to all-X
PwmSignal = 0;
counter = 0;
forever @(posedge clock) begin
PwmSignal <= (counter < PwmValue);
counter = counter + 1;
end
end

HTH
--
Jonathan Bromley

 

[Jonathan Bromley]

On Wed, 30 Dec 2009 22:59:36 +0100, Jonathan Bromley wrote:

As an example, here's a little piece of Verilog that creates
a PWM signal (n/256) under control of a system clock. You

Afterthought: I don't want to give a misleading impression.
The code I presented was very nearly synthesisable logic.
You can also create a completely asynchronous PWM generator
in a testbench; there's no need to make it look like clocked
logic. This code is a reasonable example of the kind of
very software-like things you can do in a testbench.

parameter PwmPeriod = 2000; // time units
parameter PwmMax = 256;
integer PwmValue; // 0..PwmMax, but out-of-range is OK
reg PwmSignal;

initial begin : AsyncPwmGenerator
integer PwmHighTime;
PwmValue = 0;
PwmSignal = 0;
forever begin // this happens once per PwmPeriod
PwmHighTime = (PwmValue * PwmPeriod) / PwmMax;
if (PwmHighTime > PwmPeriod) PwmHighTime = PwmPeriod;
if (PwmHighTime < 0) PwmHighTime = 0;
// generate high phase
if (PwmHighTime > 0) begin
PwmSignal = 1;
#(PwmHighTime);
end
// generate low phase
if (PwmHighTime < PwmPeriod) begin
PwmSignal = 0;
#(PwmPeriod - PwmHighTime);
end
end
end
--
Jonathan Bromley

 

[asparnique]

Hi Johnathan,

Yes, thanks for the confirmation. The test bench would need to simulate an
approximation to a real signal, however the final tests will require a more
representative signal, one that is in effect as close as possible to the
analogue signal that will be used as an input. This input is effectively a
modulated PWM, with the modulation signal a pure analogue signal of a low
frequency (say 10Hz to 1MHz etc). Such a signal could be digitized and the
equivalent PWM could be stored in a large data file on disk etc.
I then presume a test bench could use this external data file as an input to
clock in, asyncronously, the PWM for the simulation to process and generate
the desired result. These results would confirm the correctly functionning
hardware.
The approach of having signals representing analogue signals, is that a very
wide range of data can be used to test every possible input input signal
that could possibly exist under real world conditions. A simple PWM
increasing pulse width up/down is ok to start with, but later a more
representative PWM will need to be used.
So in brief my question relates to using an external data file that holds
timing data of a signal that can be loaded by the test bench verilog to
test/simulate the hardware etc. Is this easily possible would you say ?

Regards, M
"Jonathan Bromley" wrote in message
news:8sinj5tg0ls9qvpb240eflgmjdn3riove6@4ax.com...

On Wed, 30 Dec 2009 19:22:07 +0100, "asparnique" wrote:

I was wondering if there is a way to generate PWM signals for testing
verilog code ?

Sure.

More so if there is a way to use as test signals, digitized
PWM signals as input signals for testing/simulating verilog code, such as
using a data file which represents a real PWM signal for instance ??

This is exactly the sort of thing you would expect to find
in a "test bench" - an additional (possibly quite large) piece of
Verilog code that simulates the behaviour of external signals that
provide inputs to your design under test (DUT), and checks that
the DUT's outputs have appropriate values at all times.

As an example, here's a little piece of Verilog that creates
a PWM signal (n/256) under control of a system clock. You
could use it as part of a testbench. Other parts of the
testbench would create the clock signal, and manipulate the
PwmValue variable to control what this generator does.
You could then connect PwmSignal to an input of your DUT.

// assume signal "clock" exists already in the testbench

integer PwmValue; // keep this in the range 0..256
reg PwmSignal; // this is the generated PWM test signal

initial begin : PwmGeneratorBlock
reg [7:0] counter;
PwmValue = 0; // because integers initialize to all-X
PwmSignal = 0;
counter = 0;
forever @(posedge clock) begin
PwmSignal <= (counter < PwmValue);
counter = counter + 1;
end
end

HTH
--
Jonathan Bromley

 

[Jonathan Bromley]

On Thu, 31 Dec 2009 13:50:40 +0100, "asparnique" wrote:

analogue signal that will be used as an input. This input is effectively a
modulated PWM, with the modulation signal a pure analogue signal of a low
frequency (say 10Hz to 1MHz etc). Such a signal could be digitized and the
equivalent PWM could be stored in a large data file on disk etc.

Sure; but it may be easier to store the digitized analogue signal
in a file, and reconstruct the PWM from it within the testbench.

I then presume a test bench could use this external data file as an input to
clock in, asyncronously, the PWM for the simulation to process

Yes, no problem.

The approach of having signals representing analogue signals, is that a very
wide range of data can be used to test every possible input input signal
that could possibly exist under real world conditions. A simple PWM
increasing pulse width up/down is ok to start with, but later a more
representative PWM will need to be used.

Random testing (with suitable shaping and constraints) may
be even better, and is often less troublesome to set up.

So in brief my question relates to using an external data file that holds
timing data of a signal that can be loaded by the test bench verilog to
test/simulate the hardware etc. Is this easily possible would you say ?

Yes.

Verilog has two distinct ways to read data files: the traditional
$readmemb/$readmemh mechanism that has been around since the
earliest days, and the more C-like file I/O functions that were
added in Verilog-2001 (although they had been available as
vendor-supplied and public-domain extensions for some time
before that).

I still retain a certain retro-style fondness for $readmem*
because it's so very simple to set up and to use. You need...

- an array variable in your Verilog; any size, any width, but
you must KNOW the size and width:

reg [13:0] my_array[0:4]; // 5 elements, each 14 bits

- a plain-text file containing whitespace-separated numeric
values, either in binary or in hex, with optional Verilog
comments and optional underscores in the numbers:

// start of text file "values.bin"
001000_1111_0000 // 6+4+4 bits = 14 bits - that's element 0
101010_0000_1111 // element 1
000000_1010_0000 111111_0000_1111 // elements 2, 3
111111_1111_1111 // element 4
// end of text file

- a simple call to the system task $readmemb:

initial begin
$readmemb("values.bin", my_array);
... do other things with my_array
end

(And, of course, $readmemh if the data is in hex.)

Of course, you would normally create the text file's contents
from some other program or script; a straightforward task.
Check the Verilog LRM for full details of $readmem* options.

The newer file I/O functions work in a rather similar way
to file I/O in C, but there are many differences of detail
mainly because strings in Verilog are such strange beasts.
Any good Verilog tutorial, course or textbook should provide
full information.

Once you have numbers in your simulation you can do
anything you want with them - they can represent time delays,
PWM amplitude, you name it. When using $readmem*, don't forget
that you can put very wide bit-vectors into the file and use
fields of those vectors to represent different information.
For example, go back to my example of 14-bit values in the file.
If we think of the top 6 bits as being a cycle count, and
the lower 8 bits as a PWM amplitude, you could implement
your PWM generator thus:

initial begin : generator
integer i;
reg [5:0] count;
reg [7:0] amplitude;
$readmemb("values.bin", my_array);
for (i=0; i<5; i=i+1) begin // scan the array
{count, amplitude} = my_array;
repeat (count) begin
// generate one cycle of PWM with chosen amplitude
end
end
end

Hope this helps
--
Jonathan Bromley