Generating a desired synthesizable binary pulse train on FPG

[rickman]

On 7/29/2014 3:37 PM, mnentwig wrote:

Yes, thanks. I registered once, maybe I'll have a look through the
archives.

Perhaps you could start a discussion about what you are doing? I think
they have some pretty knowledgeable people there... although one fellow
tried to tell me that he could add a pipeline register on the negative
clock edge and it would work as well as one on the positive edge. I'm
not sure what he meant.

That reminds me of another way to work around the sync memory problem.
The memory can be run on the opposite phase of the clock so that it
writes and reads in the middle of the clock cycle. The timing specs
have to be set up for this and it may require some optimization to meet
timing, but it should work. I had forgotten all about this.

--

Rick

 

[mnentwig]

>> sync memory problem.

True... Spartan 6 BRAM manual states
>> The read and write operations are synchronous and require a clock edge

Anyway, I would stay away from anything that's non-standard (at least
_think_ this is unusual, with the exception of off-chip DDR).

>Perhaps you could start a discussion about what you are doing?
There isn't really a lot to discuss on the processor side: A plain ol' CPU
where FPGA RTL stuff is controlled via registers.
It's some MIDI synthesizer thing, I'm coding up my own '69 Vox Continenta
replica, an open-ended holiday/self-study project.
The only performance bottleneck is on key events, when the CPU suddenl
needs to update many virtual key contacts. Ideally I'd like to model switc
bounce in software, but probably I'll do it in RTL and then everything els
can be really slow, thanks to the low MIDI baudrate,



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Posted through http://www.FPGARelated.com

 

[Daniel Kho]

On Wednesday, 23 July 2014 00:49:52 UTC+8, chaitanya163 wrote:

Hello Everyone



I am new to VHDL programming and FPGA.

I have a Virtex - 4 FPGA and I wish to generate a binary pulse train of 16

pulses from FPGA using VHDL programming. My desired pulse train will be

like "1011100111101110". (min pulse width should be 30ns).

I have a clock of 100 MHz and I am able to divide the clock frequency to

get the clock of 10MHz (clock frequency required for my application). Also

I am aware of the fact that "Wait for" statement can not be used for

synthesizing as it can only be used for test bench and simulation purposes.





So I am struggling with this problem. I am wondering if I can use "after

Xns" command in my VHDL code or if there is any other way to do it.



I will be very thankful if any feedback or advice is provided. Your

response will truly be appreciated. Kindly provide your valuable

suggestions.



Thanking you

Regards

Chaitanya Mauskar







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Posted through http://www.FPGARelated.com

I'd write the shift register similar to the following, assuming you have your frequency divider working correctly. Some tools implement this with a 16:1 mux, which is fine.

entity shifter is port(clk,en,reset:in std_ulogic; qut std_ulogic);
end entity shifter;

architecture rtl of shifter is
constant s:std_ulogic_vector:=x"1011100111101110";
signal i:unsigned(3 downto 0);
begin
q<=s(to_integer(i));

process(reset,clk) is begin
if reset then i<=(others=>'0');
elsif rising_edge(clk) then
if en then i<=i+1; end if;
end if;
end process;
end architecture rtl;

-dan