"generate" question

[Steven Sharp]

Can you describe this additional capability that you believe VHDL
provides you? Assuming that a user-defined attribute is being used
in VHDL, I believe that it must be set to the value of a constant
expression. That constant expression can include values calculated
by a VHDL function that meets certain requirements.

In Verilog, an attribute can be set to the value of a constant
expression. That constant expression can include values calculated
by a Verilog function that meets certain requirements.

As far as I can see, the only difference is that attributes and
constant functions were added to Verilog more recently, so it is
less likely that a tool will have the full capabilities implemented.
In particular, the tool you are using does not provide enough to do
this yet.

Regardless of the language used, it is less convenient for a user
to have to convert numerical values into string form and use that
to set a string-valued attribute, than to use the numerical values
directly to set numeric-valued attributes. Therefore, choosing to
require string-valued attributes for this purpose would be a poor
design decision on the part of the tool implementor.

 

[Allan Herriman]

On 9 Oct 2003 10:29:20 -0700, sharp@cadence.com (Steven Sharp) wrote:

Can you describe this additional capability that you believe VHDL
provides you? Assuming that a user-defined attribute is being used
in VHDL, I believe that it must be set to the value of a constant
expression. That constant expression can include values calculated
by a VHDL function that meets certain requirements.

In Verilog, an attribute can be set to the value of a constant
expression. That constant expression can include values calculated
by a Verilog function that meets certain requirements.

As far as I can see, the only difference is that attributes and
constant functions were added to Verilog more recently, so it is
less likely that a tool will have the full capabilities implemented.
In particular, the tool you are using does not provide enough to do
this yet.

There are more differences than that.

Verilog:
- poor string generation capability in constant strings. (This would
be different if $swrite was able to make constant strings. Perhaps
we'll get lucky in the next language rev.)
- no choice of types for attribute values. (Is this correct? I think
you inferred that the value can only be an integer.)

VHDL:
- any function (without restriction) can be used to form attribute
value. This includes some (poor) built-in string manipulation
facilities, so most users roll their own in functions or arrays.
- Supports more types (although these all end up as strings in the
EDIF).

Regardless of the language used, it is less convenient for a user
to have to convert numerical values into string form and use that
to set a string-valued attribute, than to use the numerical values
directly to set numeric-valued attributes. Therefore, choosing to
require string-valued attributes for this purpose would be a poor
design decision on the part of the tool implementor.

The Xilinx tools have been using string based attributes since the
1980s. They've only been using EDIF since the mid-90s though (XNF was
used prior to that). This isn't something that is going to change, so
your arguments about "convenience" are misplaced, and (IMO) show a
lack of appreciation of the FPGA market.
(Sure, if this was being done from scratch, they'd probably use a pair
of integer attributes for placement, but that isn't the case here.)


Here's an example of some VHDL code I wrote in my last job. It shows
both styles of RLOC coords (RC and XY).
(Note that
'&' is the VHDL concatenation operator,
itoa() is a user defined function that converts a (signed) integer to
a string (it's a wrapper around integer'image),
g_fpga_family, h_placement_vernier, etc. are constants or generics
(parameters).)

....
pure function make_rloc (index : integer) return string is
begin
case g_fpga_family is
when FPGA_FAMILY_VIRTEX_2 =>
return "X" & itoa(h_placement_vernier) &
"Y" & itoa((index + v_placement_vernier) / 2);
when FPGA_FAMILY_VIRTEX_E =>
return "R" & itoa((width - index - v_placement_vernier) / 2) &
"C" & itoa(h_placement_vernier / 2) &
".S" & itoa(1 - (h_placement_vernier mod 2));
when others =>
assert FALSE
report "Unsupported FPGA family"
severity failure;
return "FPGA_FAMILY_UNDEFINED";
end case;
end make_rloc;

....

-- This line would normally be in a package somewhere
attribute rloc : string;

....

struct_adder : for i in local_sum'range generate
attribute rloc of u3 : label is make_rloc(i);
begin
....
u3 : xorcy
port map (
o => combinatorial_sum(i),
ci => carry_chain(i),
li => lut_output(i)
);
....

end generate struct_adder;

....

I'd be very interested in knowing if it is possible to translate this
to Verilog, since my current understand is that this isn't possible,
or is at least rather difficult.
(Or if it is possible, the tools won't support it.

Regards,
Allan.

 

[Allan Herriman]

On Fri, 10 Oct 2003 11:07:42 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

- any function (without restriction) can be used to form attribute
value.

Not quite. It must be a pure function. All values referenced within
the function must be known at elaboration time (i.e. static).

Regards,
Allan.

 

[Martin Euredjian]

Boy...I'll tell ya!

I think you just don't understand the subject. I don't have the time to
educate you. Oh, I know full-well that you are a Verilog standards expert.
I'm just not sure that you live in the real world. Had you attempted to be
semi-nice instead of condescending I might be inclined to make an effort.
But that would be a total waste of time.

One thing's for sure. You didn't make Cadence look good in my eyes. As a
small business owner I can't tell you that it won't affect my decisions when
it comes to considering Cadence products.

Plonk.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"



"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0310090929.189780c0@posting.google.com...

Can you describe this additional capability that you believe VHDL
provides you? Assuming that a user-defined attribute is being used
in VHDL, I believe that it must be set to the value of a constant
expression. That constant expression can include values calculated
by a VHDL function that meets certain requirements.

In Verilog, an attribute can be set to the value of a constant
expression. That constant expression can include values calculated
by a Verilog function that meets certain requirements.

As far as I can see, the only difference is that attributes and
constant functions were added to Verilog more recently, so it is
less likely that a tool will have the full capabilities implemented.
In particular, the tool you are using does not provide enough to do
this yet.

Regardless of the language used, it is less convenient for a user
to have to convert numerical values into string form and use that
to set a string-valued attribute, than to use the numerical values
directly to set numeric-valued attributes. Therefore, choosing to
require string-valued attributes for this purpose would be a poor
design decision on the part of the tool implementor.