From vhdl to verilog

[mattia]

Sorry, I don't want to be ot, but I need to translate this peace of code
from vhdl to verilog, can you help me?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity multi_instance is
generic( N: integer := 3 );
port(
key1_in: in std_logic_vector(0 to 63);
key2_in: in std_logic_vector(0 to 63);
key3_in: in std_logic_vector(0 to 63);
function_select: in std_logic; -- active when
encryption, inactive when decryption

save_out: in std_logic;
serial_data_in: in std_logic;
serial_data_out: out std_logic;

lddata: in std_logic; -- active when
data for loading is ready
ldkey: in std_logic; -- active when
key for loading is ready
out_ready: out std_logic_vector(0 to 2); --
active when encryption of data is done
reset: in std_logic;
clock: in std_logic
);
end multi_instance;

architecture rt of multi_instance is

component tdes_top is
port(
key1_in: in std_logic_vector(0 to
63);
key2_in: in std_logic_vector(0 to
63);
key3_in: in std_logic_vector(0 to
63);
function_select: in std_logic; --
active when encryption, inactive when decryption
data_in: in std_logic_vector(0 to
63);
data_out: out std_logic_vector(0 to
63);
lddata: in
std_logic; -- active when data for loading is ready
ldkey: in
std_logic; -- active when key for loading is ready
out_ready: out
std_logic; -- active when encryption of data is done
reset: in std_logic;
clock: in std_logic
);
end component;

signal sregin: std_logic_vector(0 to 64+N-2);
signal sregout: std_logic_vector(0 to 64*N-1);
signal sout: std_logic_vector(0 to 64*N-1);

begin

process( clock, reset )
begin
if reset = '1' then
sregin <= (others => '0');
sregout <= (others => '0');
else
if clock'event and clock = '1' then
sregin <= serial_data_in & sregin(0 to 64
+N-3);
if save_out = '1' then
sregout <= sout;
else
sregout <= '0' & sregout(0 to
64*N-2);
end if;
end if;
end if;
end process;


UU: for I in 0 to 2 generate
U: tdes_top port map(
key1_in => key1_in,
key2_in => key2_in,
key3_in => key3_in,
function_select => function_select,
data_in => sregin(I to 63+I),
data_out => sout(I*64 to (I+1)*64 - 1),
lddata => lddata,
ldkey => ldkey,
out_ready => out_ready(I),
reset => reset,
clock => clock );
end generate;

serial_data_out <= sregout(64*N-1);

end rt;












--
__mattia__

 

[Vince]

mattia a écrit:

Sorry, I don't want to be ot, but I need to translate this peace of code
from vhdl to verilog, can you help me?

Why?

--
Vince

 

[Dave]

On 14 Dec 2008 11:53:28 GMT, mattia <gervaz@gmail.com> wrote:
<VHDL snipped>

Try to find a copy of the book "HDL Chip Design" by Douglas J. Smith.
It shows VHDL and Verilog side-by-side, and should help you translate
VHDL to Verilog.

-Dave Pollum