T
Torsten Lauter
Guest
Our conditions:
Dear User,
thank you for your interest in our free VHDL PCI core.
The VHDL code is provided to you free of charge and we ask you not to pass
it on to any third parties.
The design has been tested and is expected to run smoothly.
However, no support or design guidance is guaranteed.
Its use is at your own risk and you take over full liability.
We reserve the right to name you/your company as reference user.
In turn, you ought to reference us as origin of the PCI core in the final
product description (e.g. manual, flyer etc.).
Code documentation is also at early stage, since the VHDL design is part of
a bigger project. Once there is time left in the project schedule, we will
round up the documentation.
To sum up the conditions:
- the code is provided free of charge
- no guarantee is given what so ever
- you agree to be named as reference user
- you must not pass the code on to third parties
- documentation is at early stage and support can not be guaranteed
- a reference (acknowledgement notice) to us as origin of the PCI core
must be included in the final product description
Finally, we would appreciate your feedback about functionality, application
scenarios, documentation and code add ons.
We ask you to agree to the conditions given above by means of an appropriate
email answer.
The VHDL PCI core will be emailed to you as soon as your compliance email
arrives.
Regards,
Torsten Lauter & Thomas Knoll
http://www.infotech.tu-chemnitz.de/~knoll/vhdl_pci_bridge/
"Rainer Buchty" <buchty@atbode100.informatik.tu-muenchen.de> schrieb im
Newsbeitrag news:c1kdrj$2h1f3$1@sunsystem5.informatik.tu-muenchen.de...
Dear User,
thank you for your interest in our free VHDL PCI core.
The VHDL code is provided to you free of charge and we ask you not to pass
it on to any third parties.
The design has been tested and is expected to run smoothly.
However, no support or design guidance is guaranteed.
Its use is at your own risk and you take over full liability.
We reserve the right to name you/your company as reference user.
In turn, you ought to reference us as origin of the PCI core in the final
product description (e.g. manual, flyer etc.).
Code documentation is also at early stage, since the VHDL design is part of
a bigger project. Once there is time left in the project schedule, we will
round up the documentation.
To sum up the conditions:
- the code is provided free of charge
- no guarantee is given what so ever
- you agree to be named as reference user
- you must not pass the code on to third parties
- documentation is at early stage and support can not be guaranteed
- a reference (acknowledgement notice) to us as origin of the PCI core
must be included in the final product description
Finally, we would appreciate your feedback about functionality, application
scenarios, documentation and code add ons.
We ask you to agree to the conditions given above by means of an appropriate
email answer.
The VHDL PCI core will be emailed to you as soon as your compliance email
arrives.
Regards,
Torsten Lauter & Thomas Knoll
http://www.infotech.tu-chemnitz.de/~knoll/vhdl_pci_bridge/
"Rainer Buchty" <buchty@atbode100.informatik.tu-muenchen.de> schrieb im
Newsbeitrag news:c1kdrj$2h1f3$1@sunsystem5.informatik.tu-muenchen.de...
In article <c1kbg6$t67$3@newsreader.mailgate.org>,
Kevin Brace <k0evinbr1ace@m2ail.c3om> writes:
|> The no-academic research restriction is there because I want to charge
|> more than $100 for research-related academic use.
Let me get this straight. The use should be
- non-commercial
- non-profit
- non-academic research
- strictly personal purposes
So who the hell should license that core? I can understand that you rule
out
commercial use, I *could* understand if you ruled out industrial research.
But ruling out academic research because you want to charge *more* from
universities is reducing the number of potential customers pretty much to
zero.
Rainer