fpga IOB

[niyander]

hello,

can some one tell me what's the use of IOB in FPGA, I have written a
floating point multiplier in VHDL and after synthesis (ISE), in the
design summery, i can see 99 IOB used, whats the use of it?
secondly how can i reduce IOB usage.

thanks

 

[Andy]

IOBs represent the FPGA physical pins. By default, most synthesis
tools will assume that ports on the top level entity become pins on
the FPGA. There is an option to disable this feature if you are just
running a trial synthesis for a module that will eventually be
embedded deeper inside your FPGA design.

Andy

 

[Rob Gaddi]

On Wed, 28 Oct 2009 05:32:55 -0700 (PDT)
niyander <mightycatniyander@gmail.com> wrote:

hello,

can some one tell me what's the use of IOB in FPGA, I have written a
floating point multiplier in VHDL and after synthesis (ISE), in the
design summery, i can see 99 IOB used, whats the use of it?
secondly how can i reduce IOB usage.

thanks

This is the second time you've asked this question; once in your
original thread, and now again right next to it. Don't do that. Also,
FPGA related questions should be directed to comp.arch.fpga, not
comp.lang.vhdl. CLV is for questions relating specifically to
VHDL. Granted it's 90% of the same people hanging out on both, but
it's a sorting issue.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[recow182]

How can I disable this feature?

 

[Andy]

On Sunday, February 9, 2014 1:56:58 AM UTC-6, recow182 wrote:
> How can I disable this feature?

It depends on your synthesis tool...

Look for a synthesis option called disable_io_insertion or similar (at least with Synplify).

Andy