FPGA design not working!

[mike]

I haven't defined any timing constraints and my design passes the timing
constraints test. Now i am looking at the warnings if anything is getting
optimized out. And i didn't know that these black boxes can create
problems, i am using many fifos and embedded rams.i'll have to check on
them.

You haven't defined any timing constraints!!!!! How could this
possibly work?

 

[Mike Treseler]

I haven't defined any timing constraints and my design passes the timing
constraints test.

It *is* easier to vault over the bar, when it is on the ground

For designs with a single clock, synthesis will
report Fmax, but for multiple clocks or
external interfaces, constraints (or luck) is required
to make the system work.

Now i am looking at the warnings if anything is getting
optimized out. And i didn't know that these black boxes can create
problems, i am using many fifos and embedded rams.i'll have to check on
them.

On 10/7/2010 10:56 AM, mike wrote:

You haven't defined any timing constraints!!!!! How could this
possibly work?

It seems that no spare luck was available in this case.

-- Mike Treseler

 

[salimbaba]

Hi Mike,

I had assigned timing constraints for the incoming clocks. I thought yo
were asking about the pad to pad and FFS timing constraints.
Also, i switched to xilinx 12.1 and the same design worked =) i have n
idea why wasn't it working on xilinx 9.1 . But life is good now with
little problem though.

When i add few signals in chipscope, my FPGA doesn't get programmed.
delete those signals and it gets programmed but now i can't debug my desig
=\ . It has been happening with me for quite some time now and i haven'
been able to figure it out. Have you ever faced this sort of problem ?

Thanks

Regards
SalimBaba

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