FPGA design not working!

[salimbaba]

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz syste
clock. The problem is that i can see the clock on the board and inside FPG
as well but no logic block in my fpga is working. I have no clue about wh
is it happening because all the timing constraints are met. Kindly give m
some pointers, i shall be thankful.


Regards
Salimbaba

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Kim Povlsen]

On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and inside FPGA
as well but no logic block in my fpga is working. I have no clue about why
is it happening because all the timing constraints are met. Kindly give me
some pointers, i shall be thankful.


Regards
Salimbaba

---------------------------------------
Posted through http://www.FPGARelated.com

Hi Salimbaba,

I think we need a little more information in order to give a concrete
answer. What kind of FPGA are you using, and how are you distributing
the clock within the FPGA? Are you using a DCM to instantiate BUFG's,
etc?

Regards, Kim

 

[salimbaba]

o yeah sorry i should've provided you ppl with more info. Well i am usin
Spartan 3 FPGA (XC3S4000) in my design and it is receiving data from a ph
at the clock speed of 125Mhz. I can latch the data at the input which i ca
see on chipscope, apart from this input signal, i cannot see any othe
logic block performing.
I am not using DCM to instantiate the BUFG's .. i tried that but sam
problem.

---------------------------------------
Posted through http://www.FPGARelated.com

Hi Salimbaba,

I think we need a little more information in order to give a concrete
answer. What kind of FPGA are you using, and how are you distributing
the clock within the FPGA? Are you using a DCM to instantiate BUFG's,
etc?

Regards, Kim

---------------------------------------
Posted through http://www.FPGARelated.com

 

[KJ]

On Oct 1, 6:28 am, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and inside FPGA
as well but no logic block in my fpga is working. I have no clue about why
is it happening because all the timing constraints are met. Kindly give me
some pointers, i shall be thankful.

- Did the simulation run correctly?
- Did you check that power at the device is correct?
- Do you have multiple clocks in your design?
- Is this a new board design or a known working board?

You've given so little information, that all one can suggest is the
basic checks

KJ

 

[Muzaffer Kal]

On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and inside FPGA
as well but no logic block in my fpga is working. I have no clue about why
is it happening because all the timing constraints are met. Kindly give me
some pointers, i shall be thankful.

Did you simulate your design? Before p&r, after p&r (last resort)? Do
you have a reset which is not arriving on hardware? Is clock really
arriving into the chip? when you say you can see the clock inside
FPGA, what do you mean? Are you forwarding it to a pin which you can
probe?
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[Morten Leikvoll]

"salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote in message
newsqydnWwUoM5EKjjRnZ2dnUVZ_oCdnZ2d@giganews.com...

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and inside
FPGA
as well but no logic block in my fpga is working. I have no clue about why
is it happening because all the timing constraints are met. Kindly give me
some pointers, i shall be thankful.

Learn the basics of the fpga editor. Here you can quickly find out if your
design has been optimized out for some reason. It is also possible to track
signals and add TP's internally with this and just rebuild the bitfile.

 

[Frank Buss]

Morten Leikvoll wrote:

Learn the basics of the fpga editor. Here you can quickly find out if your
design has been optimized out for some reason. It is also possible to track
signals and add TP's internally with this and just rebuild the bitfile.

I never needed to use a FPGA editor, but it is important to read and
understand all the warnings and trying to reduce it to 0 warnings (not
always possible, but e.g. in Quartus you can suppress unimportant warnings
to see new important ones).

--
Frank Buss, http://www.frank-buss.de
piano and more: http://www.youtube.com/user/frankbuss

 

[Nico Coesel]

Frank Buss <fb@frank-buss.de> wrote:

Morten Leikvoll wrote:

Learn the basics of the fpga editor. Here you can quickly find out if your
design has been optimized out for some reason. It is also possible to track
signals and add TP's internally with this and just rebuild the bitfile.

I never needed to use a FPGA editor, but it is important to read and
understand all the warnings and trying to reduce it to 0 warnings (not
always possible, but e.g. in Quartus you can suppress unimportant warnings
to see new important ones).

I doubt it is possible to have an fpga design without warnings using
Xilinx's software.

First thing to check is whether the done pin and other programming
pins are indicating the configuration is properly loaded. If that is
OK I'd create an output signal which is the clock divided by 256 or so
to check whether the design is at least doing something.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[salimbaba]

On Oct 1, 6:28=A0am, "salimbaba"
a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and insid
FP=
GA
as well but no logic block in my fpga is working. I have no clue abou
wh=
y
is it happening because all the timing constraints are met. Kindly giv
m=
e
some pointers, i shall be thankful.


- Did the simulation run correctly?
- Did you check that power at the device is correct?
- Do you have multiple clocks in your design?
- Is this a new board design or a known working board?

You've given so little information, that all one can suggest is the
basic checks

KJ

Hi KJ,

yeah i successfully simulated the design first and the device power up i
also correct.
Actually there are 4 clocks coming to the fpga, 2 from ethernet PHY and
from oscillators. I am latching the data on the PHY clocks and my whol
design is also working on them but i cannot see anything happening =( . an
well i have tested this board on 100 Mbps connectivity but now i am testin
it on 1Gbps but so far i haven't been able to make it work even a bit. I
did work the very first time i programmed it, but when i re-synthesized an
reimplemented to make sure it works, it stopped working. Probably differen
PAR. Any guesses ?any pointers ?
Also when i take out some debug signals on Chipscope for debuggin
purposes, sometimes my design stops working but on removal of those signal
it starts working again, do u know its reason ?

thanks
SalimBaba

---------------------------------------
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[salimbaba]

On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba"
a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and insid
FPGA
as well but no logic block in my fpga is working. I have no clue abou
why
is it happening because all the timing constraints are met. Kindly giv
me
some pointers, i shall be thankful.

Did you simulate your design? Before p&r, after p&r (last resort)? Do
you have a reset which is not arriving on hardware? Is clock really
arriving into the chip? when you say you can see the clock inside
FPGA, what do you mean? Are you forwarding it to a pin which you can
probe?
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

Hi muzaffar,
yes i have simulated my design and it works fine. i'll have to see th
reset signal,i'll check it tomorrow morning and yes the clock is comin
into the chip, i have checked it on Oscilloscope, and i used the dat
sampling clock as the chipscope master clock so yeah it is coming on chip
and i'll have to confirm the last point by forwarding it to some tes
point. I'll update it in the morning mate. Thanks a lot =)

http://www.dspia.com

---------------------------------------
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[salimbaba]

another thing is that when i don't put any kind of logic in my design i.e
simple sampling the data coming from phy and on negedge forwarding it, i
works fine but as soon as i add extra logic for the complete functioning
it stops working.

---------------------------------------
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[salimbaba]

ok here are the updates.
I took out the debug signals on test headers to see if they are working o
not, so no they don't work. I can see the clock on oscilloscope but th
counter i was incrementing on this clock doesn't show any output.
Any kind of help will be appreciated =)


Thanks
SalimBaba

---------------------------------------
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[Martin Thompson]

"salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> writes:

Hi,
I am using xiling 9.1 for my design and i am working on 125Mhz system
clock. The problem is that i can see the clock on the board and inside FPGA
as well but no logic block in my fpga is working. I have no clue about why
is it happening because all the timing constraints are met. Kindly give me
some pointers, i shall be thankful.

Some simple things:

* Is this a complex design? Have you got a simple design working on
this board? If not, stop and work on a trivial setup to get an LED to
flash (or an IO pin to toggle as seen on a 'scope)
* Did the simulation work? Go no further until it does! That
applies to the LED flash setup as well!

Once those are out of the way (or when you're deugging the LED-flash):

* Is the reset the right polarity? It's always difficult trying to make a
block work when actually it's being held in reset...
* You say you can see the clock inside the FPGA - how? Are yousure
it's clean?
* Are the power supplies good (and clean)? If you think so, tell us how you
measured this - you can't just put a voltmeter on and read the
value...

Those are fairly vague and generic - you'll have to give us more
details before we can help much further.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware

 

[Morten Leikvoll]

"Frank Buss" <fb@frank-buss.de> wrote in message
news:4p7xos2qr8et$.bo2svvm1g3ko.dlg@40tude.net...

Morten Leikvoll wrote:

Learn the basics of the fpga editor. Here you can quickly find out if
your
design has been optimized out for some reason. It is also possible to
track
signals and add TP's internally with this and just rebuild the bitfile.

I never needed to use a FPGA editor, but it is important to read and
understand all the warnings and trying to reduce it to 0 warnings (not
always possible, but e.g. in Quartus you can suppress unimportant warnings
to see new important ones).

If you want to debug efficient, you should use binary search to find issues.
Yes, you could do ALOT of tests from the beginning, like checking config
cycle, clock sources, compiler warnings (a zillion) and so on. This works
best if you are pretty sure where the error happened.

If you have no clue, the binary search is much more efficient. If FPGA
editor shows that things are not routed like you want, you can pick a new
test based on the result there. If routing looks ok, check config and clks.
If it doesnt look ok, you may track a net until you find what is optimized
out, then check warnings.

FPGA editor is also very useful to save time if you want to quickly change
minor stuff, like change slewrates, drive level, add/remove internal
pullups, add inverters and much more (depending on your skills). FPGA editor
is probably the most useful tool in there, but nobody cares to use it. Of
course, when verified, you should make sure the source files reflect what
you do in the editor, so don't release a bifile that has been edited.

 

[salimbaba]

Some simple things:

* Is this a complex design? Have you got a simple design working on
this board? If not, stop and work on a trivial setup to get an LED to
flash (or an IO pin to toggle as seen on a 'scope)

Yes this is a very complex design and i got a simple design working on thi
board. It was same design with small logic and it worked but when i adde
more logic blocks in it, it stopped working.

* Did the simulation work? Go no further until it does! That
applies to the LED flash setup as well!

yes the simulation worked successfully.

Once those are out of the way (or when you're deugging the LED-flash):

* Is the reset the right polarity? It's always difficult trying to mak
a
block work when actually it's being held in reset...

i have not declared reset in UCF file although i have it in design. Bu
that doesnt matter because it has worked with small logic blocks.

* You say you can see the clock inside the FPGA - how? Are yousure
it's clean?

yes i can see the clock inside the FPGA. I have assigned the incoming cloc
from PHY to a debug test point so yes i can see it.

* Are the power supplies good (and clean)? If you think so, tell us ho
you
measured this - you can't just put a voltmeter on and read the
value...

Yes the power supplies are good and clean. I measured them usin
oscilloscope.


regards
SalimBaba

---------------------------------------
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[Mike Treseler]

Yes this is a very complex design and i got a simple design working on this
board. It was same design with small logic and it worked but when i added
more logic blocks in it, it stopped working.

I would revert to the working design and add one module at at time.

-- Mike Treseler

 

[Frank Buss]

salimbaba wrote:

i have not declared reset in UCF file although i have it in design. But
that doesnt matter because it has worked with small logic blocks.

This could be a problem. Do you have assigned a fixed level to the reset
signal or initialized the reset signal (e.g. if you are using VHDL)?
Otherwise the synthesis tool can choose whatever level it wants, but of
course, it prints a warning for you

And you could try to assign the reset signal to a pin, maybe some
initialization doesn't work. I had this problem with a Cyclone chip and
fixed it by generating an internal reset signal a millisecond after the
FPGA starts. The advantage is that you can be sure that a normal external
reset works the same.

BTW: In my experience it is possible to reduce the warnings even in complex
designs to a handful, which then can be suppressed, to see important new
warnings.

--
Frank Buss, http://www.frank-buss.de
piano and more: http://www.youtube.com/user/frankbuss

 

[salimbaba]

Ok, i assigned a fixed level to reset so that it comes in a known state an
still the problem persists. I actually placed an internal pull down o
reset, reset is active high. And i couldn't find any warning related t
reset.

And well yes i guess i'll have to reduce the number of warnings to make i
work.
Today i also migrated to xilinx 12.1 to make sure the older version wasn'
making it a big deal for me but same result only synthesis takes less tim
which is a relief =)

I'll keep you updated so that if someone else faces this problem, he ca
take reference from here. =)

thanks mate

regards
SalimBaba

---------------------------------------
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[salimbaba]

I echo the importance of checking to see if anything was optimized
out. In FPGA editor--or simply check the PAD report--verify that every
input and output port of your top-level file is present. Make sure any
black boxes you are using (e.g. embedded ram and fifos) are
satisfactorily filled during par (typically need proper NGC file in
project directory and/or search path.

I don't think you mention anything about timing closure. Are you
defining period constraint for your clock(s)? Does static timing
analysis report that design passes all timing constraints?

Good luck.
John

Hi John,
I haven't defined any timing constraints and my design passes the timin
constraints test. Now i am looking at the warnings if anything is gettin
optimized out. And i didn't know that these black boxes can creat
problems, i am using many fifos and embedded rams.i'll have to check o
them.

Thanks John =)

regards
SalimBaba

---------------------------------------
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[jc]

On Oct 4, 3:18 pm, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

Ok, i assigned a fixed level to reset so that it comes in a known state and
still the problem persists. I actually placed an internal pull down on
reset, reset is active high. And i couldn't find any warning related to
reset.

And well yes i guess i'll have to reduce the number of warnings to make it
work.
Today i also migrated to xilinx 12.1 to make sure the older version wasn't
making it a big deal for me but same result only synthesis takes less time
which is a relief =)

I'll keep you updated so that if someone else faces this problem, he can
take reference from here. =)

thanks mate

regards
SalimBaba          

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

I echo the importance of checking to see if anything was optimized
out. In FPGA editor--or simply check the PAD report--verify that every
input and output port of your top-level file is present. Make sure any
black boxes you are using (e.g. embedded ram and fifos) are
satisfactorily filled during par (typically need proper NGC file in
project directory and/or search path.

I don't think you mention anything about timing closure. Are you
defining period constraint for your clock(s)? Does static timing
analysis report that design passes all timing constraints?

Good luck.
John