for loop in tcl of Modelsim - what's go wrong?

[Анатолий Шара]

Good day.

I've got a question of displaying in Wave window the same signals of the same modules instantiated by Verilog generate directive.
I've simplified the task as much as I could.

I'm simulating my module (for_ext), that comprise say 4 similar (coinsiding) modules (for_int). This simulation is done with test bench (for_ext_test) and tcl script (work_for_loop.do).

File for.v looks like that:

------------ start of file "for.v" --------------
`define CH_NUM 4
`define CH_NUM_RNG `CH_NUM - 1 : 0
`define PERIOD 10
`define HALF_PERIOD `PERIOD/2
`define START_RES 2
`define LENGTH_RES `PERIOD


module for_int ( input clk, res, din, output reg dout);
always @(posedge clk)
dout <= (res) ? 1'b0: din;
endmodule

module for_ext (
input clk, res,
input [`CH_NUM_RNG] din,
output [`CH_NUM_RNG] dout
);
genvar i;
generate for (i = 0; i < `CH_NUM; i = i + 1) begin: gen_block
for_int for_int_inst (.clk(clk), .res(res), .din(din), .dout(dout));
end
endgenerate
endmodule

`timescale 1ns / 100ps
module for_ext_test;
reg clk, res;
reg [`CH_NUM_RNG] din;
wire [`CH_NUM_RNG] dout;
genvar i;

for_ext for_ext_inst (.clk(clk), .res(res), .din(din), .dout(dout));

initial begin
clk = 0;
res = 0;
#`START_RES res = 1;
#`LENGTH_RES res = 0;
end

generate for (i = 0; i < `CH_NUM; i = i + 1) begin: din_init
initial
din = 0;
end
endgenerate

initial
forever #(`HALF_PERIOD) clk = !clk;

endmodule
---------------end of file "for.v"--------------------

File work_for_loop.do looks like that:
------------ start of file "work_for_loop.do" --------
quit -sim
vlog -incr -reportprogress 300 -work work_for_loop work_for_loop/for.v
vsim -voptargs=+acc work_for_loop.for_ext_test -wlfdeleteonquit

add wave -divider "for_ext_test"
add wave sim:/for_ext_test/*

for {set i 0} {$i < 3} {incr i} {
add wave -divider {"for_ext_inst[$i]"}
add wave {sim:/for_ext_test/for_ext_inst/gen_block[$i]/for_int_inst/*}
}

run 100ns
view wave -title "monitor" -undock -x 1920 -y 0 -width 1280 -height 900
wave zoom full
---------------end of file "work_for_loop.do"---------

As a result of compilation and at the start of simulation Modelsim says:

VSIM(paused)> do work_for_loop.do
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module for_int
# -- Compiling module for_ext
# -- Compiling module for_ext_test
#
# Top level modules:
# for_ext_test
# vsim -voptargs=+acc -wlfdeleteonquit work_for_loop.for_ext_test
# Loading work_for_loop.for_ext_test
# Loading work_for_loop.for_ext
# Loading work_for_loop.for_int
# ** Error: (vish-4014) No objects found matching '/for_ext_test/for_ext_inst/gen_block[$i]/for_int_inst/*'.

# Error in macro ./work_for_loop.do line 11
# (vish-4014) No objects found matching '/for_ext_test/for_ext_inst/gen_block[$i]/for_int_inst/*'.

# while executing
# "add wave {sim:/for_ext_test/for_ext_inst/gen_block[$i]/for_int_inst/*}"
# ("for" body line 3)
# invoked from within
# "for {set i 0} {$i < 3} {incr i} {
# add wave -divider {"for_ext_inst[$i]"}
# add wave {sim:/for_ext_test/for_ext_inst/gen_block[$i]/for_int_inst/*}
# }"
VSIM(paused)>

/////////////////////////////////////////////////////////

So my question is:
how can I display at waiveform internals of all of my modules, using some tcl loop statements? Is it possible in Modelsim invironment?

Thank you for you time and help in advance.

Regards, Anatoly.