Flatten Verilog netlist

[Kenneth Brun Nielsen]

Any suggestions for how I can flatten a hierarchical Verilog netlist?
Any tools for the purpose?

Best regards,
Kenneth

 

[Jonathan Bromley]

On Mon, 3 Jan 2011 06:03:10 -0800 (PST), Kenneth Brun Nielsen
<kenneth.brun.nielsen@googlemail.com> wrote:

Any suggestions for how I can flatten a hierarchical Verilog netlist?
Any tools for the purpose?

Read it into a synthesis tool, don't do any optimization (just
let the tool elaborate it) and then get it to write out in
Verilog with the tool's flatten-hierarchy option switched on?
--
Jonathan Bromley

 

[Kenneth Brun Nielsen]

On 3 Jan., 15:24, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Mon, 3 Jan 2011 06:03:10 -0800 (PST), Kenneth Brun Nielsen

kenneth.brun.niel...@googlemail.com> wrote:
Any suggestions for how I can flatten a hierarchical Verilog netlist?
Any tools for the purpose?

Read it into a synthesis tool, don't do any optimization (just
let the tool elaborate it) and then get it to write out in
Verilog with the tool's flatten-hierarchy option switched on?

I don't have access to a synthesis tool - does some freeware exist
with that option?

Best regards,
Kenneth

 

[Jonathan Bromley]

On Mon, 3 Jan 2011 07:35:56 -0800 (PST), Kenneth Brun Nielsen wrote:

Any suggestions for how I can flatten a hierarchical Verilog netlist?

Read it into a synthesis tool, [...]

I don't have access to a synthesis tool - does some freeware exist
with that option?

If your Perl is quite a bit better than mine, you might like to
take a look at Wilson Snyder's Verilog-manipulation tools at
www.veripool.org/wiki/verilog-perl

Netlists are often created using a fairly simple subset of
Verilog, so it may be possible to write a custom parser that
will construct the hierarchy and write it out again in flat
organization. For netlists generated by synthesis tools,
that may be fairly straightforward. Some features of
Verilog may make it harder, though - defparam is an obvious
trip-wire.
--
Jonathan Bromley

 

[Nikolaos Kavvadias]

Hi Kenneth

On Jan 3, 5:35 pm, Kenneth Brun Nielsen
<kenneth.brun.niel...@googlemail.com> wrote:

I don't have access to a synthesis tool - does some freeware exist
with that option?

Given that you have sufficient bandwidth you should be able to
download free-of-charge versions for
popular logic synthesis tools such as Xilinx ISE 12.4 (beware huge
download ~8GB!) or Altera Quartus-II.
Even an older Xilinx ISE "Webpack" (I recall these being around 100MB
8-9 years ago; maybe series 6.3?)
might come handy.

The bad news: No great open-source synthesizers out there especially
for FPGAs.

Somewhat-related projects involve:
Icarus Verilog (has some FPGA device backends, probably old)
fpgac at sourceforge
Signs (development stopped at 0.6.3?)

There exist a couple ASIC synthesizers (e.g. Alliance and Electric)
but those
might not be directly useful to you.

Lastly, some academic tools handling BLIF, EDIF or XNF netlists do
lurk out there in the wild.
Again, not sure if these could suit your needs.

Best regards
Nikolaos Kavvadias

 

[Kenneth Brun Nielsen]

On Jan 3, 6:58 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Mon, 3 Jan 2011 07:35:56 -0800 (PST), Kenneth Brun Nielsen wrote:
Any suggestions for how I can flatten a hierarchical Verilog netlist?

Read it into a synthesis tool, [...]

I don't have access to a synthesis tool - does some freeware exist
with that option?

If your Perl is quite a bit better than mine, you might like to
take a look at Wilson Snyder's Verilog-manipulation tools at
 www.veripool.org/wiki/verilog-perl

Netlists are often created using a fairly simple subset of
Verilog, so it may be possible to write a custom parser that
will construct the hierarchy and write it out again in flat
organization.  For netlists generated by synthesis tools,
that may be fairly straightforward.  Some features of
Verilog may make it harder, though - defparam is an obvious
trip-wire.

Yes, I tried to build a quick-and-dirty hierarchy-traverser, but it
seems to be very limited in the source-code replication. E.g. all
initial and always statements seems to be removed when I use the
module->verilog_text function. That's really a shame, because it would
be close-to-perfect for the job, if it did not have this limitation.


--
use Verilog::Netlist;

# Setup options so files can be found
use Verilog::Getopt;
my $opt = new Verilog::Getopt;
$opt->parameter( "+incdir+verilog",
"-y","verilog",
);

# Prepare netlist
my $nl = new Verilog::Netlist (options => $opt,);
foreach my $file ('VERILOG/file1.v', 'VERILOG/file2.v') {
$nl->read_file (filename=>$file);
}
# Read in any sub-modules
$nl->link();
$nl->exit_if_error();

foreach my $mod ($nl->top_modules_sorted) {
# printf ("TOPMODULE: %s \n", $mod->name);
if ($mod->name eq "RELEVANT_TOP_MODULE_NAME") {
show_hier ($mod, " ", "", "");
my @codeArray = $mod->verilog_text;
print @codeArray;
}
}

sub show_hier {
my $mod = shift;
my $indent = shift;
my $hier = shift;
my $cellname = shift;
if (!$cellname) {$hier = $mod->name;} #top modules get the design
name
else {$hier .= ".$cellname";} #append the cellname
printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
foreach my $sig ($mod->ports_sorted) {
printf ($indent." %sput %s\n", $sig->direction, $sig->name);
}
foreach my $cell ($mod->cells_sorted) {
printf ($indent. " Cell %s\n", $cell->name);
foreach my $pin ($cell->pins_sorted) {
printf ($indent." .%s(%s)\n", $pin->name, $pin->netname);
}
show_hier ($cell->submod, $indent." ", $hier, $cell->name) if
$cell->submod;
}
--

Thanks for your replies

Best regards,
Kenneth

 

[Kenneth Brun Nielsen]

On Jan 3, 6:59 pm, Nikolaos Kavvadias <nikolaos.kavvad...@gmail.com>
wrote:

Hi Kenneth

On Jan 3, 5:35 pm, Kenneth Brun Nielsen

kenneth.brun.niel...@googlemail.com> wrote:
I don't have access to a synthesis tool - does some freeware exist
with that option?

Given that you have sufficient bandwidth you should be able to
download free-of-charge versions for
popular logic synthesis tools such as Xilinx ISE 12.4 (beware huge
download ~8GB!) or Altera Quartus-II.
Even an older Xilinx ISE "Webpack" (I recall these being around 100MB
8-9 years ago; maybe series 6.3?)
might come handy.

The bad news: No great open-source synthesizers out there especially
for FPGAs.

Somewhat-related projects involve:
Icarus Verilog (has some FPGA device backends, probably old)
fpgac at sourceforge
Signs (development stopped at 0.6.3?)

There exist a couple ASIC synthesizers (e.g. Alliance and Electric)
but those
might not be directly useful to you.

Lastly, some academic tools handling BLIF, EDIF or XNF netlists do
lurk out there in the wild.
Again, not sure if these could suit your needs.

Hi Nikolaos,

Do you know if any of them have the necessary options for hierarchy
flattening? I looked at the Icarus FPGA target, but it doesn't occur
very useful. My task is not to synthesize, but to generate a flat
netlist in order to manipulate it with "stuck-at-values" on selected
nets (the big task is to make a measure for test coverage).

Best regards,
Kenneth