favorite Spice speedups...

[Joe Gwinn]

On Tue, 25 Oct 2022 21:56:32 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

Joe Gwinn wrote:
On Tue, 25 Oct 2022 18:01:17 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

Joe Gwinn wrote:
On Tue, 25 Oct 2022 07:56:38 -0700, John Larkin
jlarkin@highlandSNIPMEtechnology.com> wrote:

On Tue, 25 Oct 2022 10:43:18 -0400, bitrex <user@example.net> wrote:

On 10/24/2022 4:16 PM, John Larkin wrote:
We have some sims that run absurdly slow. What are your favorite
speedups?

In LT spice, I have arbitrarily done

.opt reltol=.002

.opt abstol=5n

.opt trtol=5

but that\'s just guessing. It may work with my parts but mess up an
encrypted model that I have no visibility into.

Sometimes one solver is unaccountably better than another.


Using a RAM drive for waveform storage is one, but I guess I don\'t
regularly run sims complex enough that it causes a Ryzen 5600 to chug
badly enough to make me frustrated. Have you upgraded your CPU lately?

The guy running this for me has a pretty good, fairly new PC. But the
sim takes hours to simulate 10s of milliseconds, so we don\'t want a
modest speedup.

TI software, TI models, runs for hours. That\'s silly.

My recollection from my power-system colleagues is that this can be
caused by often parasitic sub circuits with very short time constants
(compared to the core circuit), so the approach was to model only the
core circuit at first, then start to decorate it.

Joe Gwinn

The Gear integrator is specifically designed for problems like that.
(\"stiff systems\").

Yes, but sometimes one must also simplify.

I\'ve also been bitten by MATLAB handling an overdetermined system by
endless iteration. Had to reformulate the problem to evade that.

Joe Gwinn


A stiff system is one whose largest and smallest eigenvalues are very
different, in some not-too-well-defined mathematical notion of \"very
different\".

Yes. In a realistic power-supply circuit models, the parasitic
subcircuits will have eigen frequencies far higher than the core
circuits, so the overall system is stiff.

An overdetermined system is another animal--usually a benevolent one
IME. With a bit of work, it\'s often possible to get a least-squares
optimum solution plus an internal error estimate.

Yes, solving inherently overdetermined systems can be quite useful.

The problem we had was that the sim was running a factor of about a
hundred slower than needed to permit the required sim runs to be made
in time, and the over determination was an accident of how the
simulation was structured. It was expressed in a block-and-wire model
(Simulink, no programming needed!), and looked clean and simple on
paper. Oops.

Fifth- and higher-order Runge-Kutta methods for ODEs are an example I
recall, and of course closure phase in interferometry.

Oh, yes. What I also recall using was implicit numerical integration,
like Backward Euler:

..<https://en.wikipedia.org/wiki/Explicit_and_implicit_methods>

The advantage being that the simple implicit methods were not all that
fussy.

Joe Gwinn

 

[John Larkin]

On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
<\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.

We once did some awkward PDE\'s in a computer solution and on a Tektronix
vector display monitor they looked fine so sent them off to the plotter.
The job came back part done with an apologetic note from the sysop \"your
job was cancelled because the red pen began to work loose\".

Careful examination of the plot file showed some of the vector steps
were just Angstroms long!

Sometimes a Spice sim takes femtosecond steps all afternoon. For some
reason the Spice programs allow us to set the max time step but not
the min.

Usually if a simulation goes to insanely short steps it is because it
cannot achieve the specified accuracy any other way (or is buggy). That
sort of behaviour is characteristic of stiff equations where it is
fighting hard to prevent the solution diverging in some bad way.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.

 

[Phil Hobbs]

John Larkin wrote:

On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.





We once did some awkward PDE\'s in a computer solution and on a Tektronix
vector display monitor they looked fine so sent them off to the plotter.
The job came back part done with an apologetic note from the sysop \"your
job was cancelled because the red pen began to work loose\".

Careful examination of the plot file showed some of the vector steps
were just Angstroms long!

Sometimes a Spice sim takes femtosecond steps all afternoon. For some
reason the Spice programs allow us to set the max time step but not
the min.

Usually if a simulation goes to insanely short steps it is because it
cannot achieve the specified accuracy any other way (or is buggy). That
sort of behaviour is characteristic of stiff equations where it is
fighting hard to prevent the solution diverging in some bad way.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.

I suspect they give their modelers tight budgets for how many hours they
can spend per model.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Wed, 26 Oct 2022 15:29:06 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.





We once did some awkward PDE\'s in a computer solution and on a Tektronix
vector display monitor they looked fine so sent them off to the plotter.
The job came back part done with an apologetic note from the sysop \"your
job was cancelled because the red pen began to work loose\".

Careful examination of the plot file showed some of the vector steps
were just Angstroms long!

Sometimes a Spice sim takes femtosecond steps all afternoon. For some
reason the Spice programs allow us to set the max time step but not
the min.

Usually if a simulation goes to insanely short steps it is because it
cannot achieve the specified accuracy any other way (or is buggy). That
sort of behaviour is characteristic of stiff equations where it is
fighting hard to prevent the solution diverging in some bad way.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours they
can spend per model.

Cheers

Phil Hobbs

One of my guys managed to get the TI switchers to run in LT Spice.

Then managed to speed it up. As in, add a milliohm of ESR to the
bootstrap cap. Things like that.

 

[Phil Hobbs]

John Larkin wrote:

On Wed, 26 Oct 2022 15:29:06 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.





We once did some awkward PDE\'s in a computer solution and on a Tektronix
vector display monitor they looked fine so sent them off to the plotter.
The job came back part done with an apologetic note from the sysop \"your
job was cancelled because the red pen began to work loose\".

Careful examination of the plot file showed some of the vector steps
were just Angstroms long!

Sometimes a Spice sim takes femtosecond steps all afternoon. For some
reason the Spice programs allow us to set the max time step but not
the min.

Usually if a simulation goes to insanely short steps it is because it
cannot achieve the specified accuracy any other way (or is buggy). That
sort of behaviour is characteristic of stiff equations where it is
fighting hard to prevent the solution diverging in some bad way.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours they
can spend per model.

Cheers

Phil Hobbs

One of my guys managed to get the TI switchers to run in LT Spice.

Then managed to speed it up. As in, add a milliohm of ESR to the
bootstrap cap. Things like that.

Sounds super useful. Get him to post it at the LTspice group.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Mike Monett VE3BTI]

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

Then managed to speed it up. As in, add a milliohm of ESR to the
bootstrap cap. Things like that.


Sounds super useful. Get him to post it at the LTspice group.

Cheers

Phil Hobbs

It\'s worth noting that LTspice adds 1 milliohm of series resistance to
inductors. You can change it, of course.

The trick is it doesn\'t add any series resistance to capacitors. This traps
most people who are not aware of the difference, and some wild simulations
result.



--
MRM

 

[Anthony William Sloman]

On Thursday, October 27, 2022 at 1:18:34 PM UTC+11, Mike Monett VE3BTI wrote:

Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

Then managed to speed it up. As in, add a milliohm of ESR to the
bootstrap cap. Things like that.


Sounds super useful. Get him to post it at the LTspice group.

It\'s worth noting that LTspice adds 1 milliohm of series resistance to
inductors. You can change it, of course.

The trick is it doesn\'t add any series resistance to capacitors. This traps
most people who are not aware of the difference, and some wild simulations
result.

Capacitors range from 1pF to hundred of uF. It\'s a large range and one size wouldn\'t fit all.

--
Bill Sloman, Sydney

 

[Mike Monett VE3BTI]

Mike Monett VE3BTI <spamme@not.com> wrote:

The trick is it doesn\'t add any series resistance to capacitors. This
traps most people who are not aware of the difference, and some wild
simulations result.

The moral of the story is always, always add series resistance to capacitors,
and adjust the inductor series resistance to the appropriate value.

This gets complicated if skin effect is involved, since it changes with
frequency. But there are various models for skin effect that can be used.



--
MRM

 

[John Larkin]

On Wed, 26 Oct 2022 21:00:14 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin wrote:
On Wed, 26 Oct 2022 15:29:06 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.





We once did some awkward PDE\'s in a computer solution and on a Tektronix
vector display monitor they looked fine so sent them off to the plotter.
The job came back part done with an apologetic note from the sysop \"your
job was cancelled because the red pen began to work loose\".

Careful examination of the plot file showed some of the vector steps
were just Angstroms long!

Sometimes a Spice sim takes femtosecond steps all afternoon. For some
reason the Spice programs allow us to set the max time step but not
the min.

Usually if a simulation goes to insanely short steps it is because it
cannot achieve the specified accuracy any other way (or is buggy). That
sort of behaviour is characteristic of stiff equations where it is
fighting hard to prevent the solution diverging in some bad way.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours they
can spend per model.

Cheers

Phil Hobbs

One of my guys managed to get the TI switchers to run in LT Spice.

Then managed to speed it up. As in, add a milliohm of ESR to the
bootstrap cap. Things like that.


Sounds super useful. Get him to post it at the LTspice group.

Cheers

Phil Hobbs

I\'ll clean it up some and post here at least.

The TPS54302 sim runs at bearable speed, but efficiency is mediocre.
It\'s pulling 6T amps on the +12 input.

 

[Martin Brown]

On 26/10/2022 20:29, Phil Hobbs wrote:

John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a
bit of
spurious dissipation 1M to ground here and there might take the
edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.

What might break the deadlock for computation is add a small series
resistance to the capacitance after the first regulator to low pass
filter it. The trick will be to find something modest enough to not
affect the predictions much but sufficient to compute it more easily.

You might have to do something like that IRL too.

I expect they never expected you to daisy chain them back to back like
that and the output of the first one really doesn\'t like facing the
negative impedance dynamic load. Classic way to make an oscillator.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours they
can spend per model.

And that they never considered the output of one driving the inputs of
several others.

--
Regards,
Martin Brown

 

[Phil Hobbs]

Martin Brown wrote:

On 26/10/2022 20:29, Phil Hobbs wrote:
John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the
time step is becoming infinitessimal on one of the rapid
transitions. Adding a bit of spurious dissipation 1M to
ground here and there might take the edge off whatever is
making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher
chip models.

We just discovered that their TPS562208 model runs about 50x
faster than the TPS54302 model. They are very similar chips.
We have both in our power supply design, one 54302
pre-regulating for three of the 562208\'s.

It might be worth building one to see if it really is inclined
to squeg in real circuits. The sim could be telling you
something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the
three secondary switchers, negative impedance loads, making the
first one oscillate. That\'s not a risk we want on our new delay
generator.

Each reg needs output caps of unknown value, and feedforward caps
in its fedback divider. May as well get all that right.

What might break the deadlock for computation is add a small series
resistance to the capacitance after the first regulator to low pass
filter it. The trick will be to find something modest enough to not
affect the predictions much but sufficient to compute it more
easily.

You might have to do something like that IRL too.

I expect they never expected you to daisy chain them back to back
like that and the output of the first one really doesn\'t like facing
the negative impedance dynamic load. Classic way to make an
oscillator.

Parasitic things with ridiculously high Q can ring if provoked
which is why adding the odd spurious dissipative resistor to
certain key nodes sometimes helps instil good behaviour. Jeroen
has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours
they can spend per model.

And that they never considered the output of one driving the inputs
of several others.

Yup.

The misbehaviour there happens at the timescale of the loop bandwidth,
so it shouldn\'t run pathologically slowly on that account.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Thu, 27 Oct 2022 13:46:47 +0100, Martin Brown
<\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 20:29, Phil Hobbs wrote:
John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a
bit of
spurious dissipation 1M to ground here and there might take the
edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.

What might break the deadlock for computation is add a small series
resistance to the capacitance after the first regulator to low pass
filter it. The trick will be to find something modest enough to not
affect the predictions much but sufficient to compute it more easily.

You might have to do something like that IRL too.

I expect they never expected you to daisy chain them back to back like
that and the output of the first one really doesn\'t like facing the
negative impedance dynamic load. Classic way to make an oscillator.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours they
can spend per model.

And that they never considered the output of one driving the inputs of
several others.

Here\'s what I have so far. The first switcher sees a complex load,
some of which is negative impedance. We\'ll split the board into noisy
and quiet \"Q\" halves with ferrite beads bridging the power pours. That
makes the impedances yet more interesting.

https://www.dropbox.com/s/pklyt3mrlvf3ewm/28S662A7_power.pdf?dl=0

I hope it\'s not that ratty in real life, and is somewhat more
efficient.

This being 2022, the design is dominated by what we can get.

We have managed to get the TI switchers to work in LT Spice at
bearable speeds, tens of minutes per run instead of overnight. I don\'t
trust the results, especially for the first switcher, the TPS54302.

https://www.dropbox.com/s/sd5640vv8et0jb1/TPS54302_Sim_JL1.jpg?raw=1

The sim log file is full of complaints about bad curly brackets and
such. I didn\'t draw any curly brackets.

Switchers driving switchers is common. Nobody likes going from 24
volts to 1 volt, even if you can get the parts.

Go to the TI or ADI web site and look at New Products. It\'s mind
boggling. How can they support, and make good models for, all those
parts? How long will they keep making them?

 

[Jan Panteltje]

33On a sunny day (Thu, 27 Oct 2022 08:09:08 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<166llh58sb6stk1rrg9au34otiomeuu6me@4ax.com>:

Here\'s what I have so far. The first switcher sees a complex load,
some of which is negative impedance. We\'ll split the board into noisy
and quiet \"Q\" halves with ferrite beads bridging the power pours. That
makes the impedances yet more interesting.

https://www.dropbox.com/s/pklyt3mrlvf3ewm/28S662A7_power.pdf?dl=0

I hope it\'s not that ratty in real life, and is somewhat more
efficient.

This being 2022, the design is dominated by what we can get.

We have managed to get the TI switchers to work in LT Spice at
bearable speeds, tens of minutes per run instead of overnight. I don\'t
trust the results, especially for the first switcher, the TPS54302.

https://www.dropbox.com/s/sd5640vv8et0jb1/TPS54302_Sim_JL1.jpg?raw=1

The sim log file is full of complaints about bad curly brackets and
such. I didn\'t draw any curly brackets.

The sim has C7 1 nF to ground, not in the circuit diagram?

Switchers driving switchers is common. Nobody likes going from 24
volts to 1 volt, even if you can get the parts.

Well walwarts go from 230 V to 6 V etc, ratio even more
So do my Meanwells from 230 V to 7 V
Maybe the word is \'transformer\' here..

Ringcores are cool:
http://panteltje.com/pub/drone_power_small_core_test_detail_IMG_6115.JPG

But maybe too big for that thing you have?
OTOH BAD things must happen for those parts not to be around anymore

That was to keep my drone airborne via a thin coax carrying high voltage
transformed back to 7V at the drone:
http://panteltje.com/pub/drone_power_small_core_test_IMG_6114.JPG
http://panteltje.com/pub/h501s_drone_remote_power_flight_test_1_IMG_6274.JPG
http://panteltje.com/pub/h501s_drone_remote_power_test_ground_control_1_IMG_6276.JPG

 

[John Larkin]

On Thu, 27 Oct 2022 15:56:30 GMT, Jan Panteltje
<pNaonStpealmtje@yahoo.com> wrote:

33On a sunny day (Thu, 27 Oct 2022 08:09:08 -0700) it happened John Larkin
jlarkin@highlandSNIPMEtechnology.com> wrote in
166llh58sb6stk1rrg9au34otiomeuu6me@4ax.com>:

Here\'s what I have so far. The first switcher sees a complex load,
some of which is negative impedance. We\'ll split the board into noisy
and quiet \"Q\" halves with ferrite beads bridging the power pours. That
makes the impedances yet more interesting.

https://www.dropbox.com/s/pklyt3mrlvf3ewm/28S662A7_power.pdf?dl=0

I hope it\'s not that ratty in real life, and is somewhat more
efficient.

This being 2022, the design is dominated by what we can get.

We have managed to get the TI switchers to work in LT Spice at
bearable speeds, tens of minutes per run instead of overnight. I don\'t
trust the results, especially for the first switcher, the TPS54302.

https://www.dropbox.com/s/sd5640vv8et0jb1/TPS54302_Sim_JL1.jpg?raw=1

The sim log file is full of complaints about bad curly brackets and
such. I didn\'t draw any curly brackets.

The sim has C7 1 nF to ground, not in the circuit diagram?

I think that is just to get the sim un-stalled. As is the 100m ESR of
the bootstrap cap.

Switchers driving switchers is common. Nobody likes going from 24
volts to 1 volt, even if you can get the parts.

Well walwarts go from 230 V to 6 V etc, ratio even more
So do my Meanwells from 230 V to 7 V
Maybe the word is \'transformer\' here..

Yes. High ratio transformers help.

Ringcores are cool:
http://panteltje.com/pub/drone_power_small_core_test_detail_IMG_6115.JPG

But maybe too big for that thing you have?

I am struggling for every square mm of board area.

>OTOH BAD things must happen for those parts not to be around anymore

Parts seem to be available more lately, especially direct from TI.

That was to keep my drone airborne via a thin coax carrying high voltage
transformed back to 7V at the drone:
http://panteltje.com/pub/drone_power_small_core_test_IMG_6114.JPG
http://panteltje.com/pub/h501s_drone_remote_power_flight_test_1_IMG_6274.JPG
http://panteltje.com/pub/h501s_drone_remote_power_test_ground_control_1_IMG_6276.JPG

I tested a 30 ga twisted pair of magnet wire. It failed at 1400 volts.
Wire-wrap wire must be 10 KV-ish. You\'d need a clever HV downconverter
to use really light wire.

How about a single wire to power a drone?

 

[Kevin Aylward]

\"Martin Brown\" wrote in message news:tjap6l$4vg$1@gioia.aioe.org...

On 26/10/2022 04:41, John Larkin wrote:

On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

We once did some awkward PDE\'s in a computer solution and on a Tektronix
vector display monitor they looked fine so sent them off to the plotter.
The job came back part done with an apologetic note from the sysop \"your
job was cancelled because the red pen began to work loose\".

Careful examination of the plot file showed some of the vector steps
were just Angstroms long!

Sometimes a Spice sim takes femtosecond steps all afternoon. For some
reason the Spice programs allow us to set the max time step but not
the min.

Usually if a simulation goes to insanely short steps it is because it
cannot achieve the specified accuracy any other way (or is buggy).

Yes.

That sort of behaviour is characteristic of stiff equations where it is
fighting hard to prevent the solution diverging in some bad way.

I have to disagree on the claim about stiff equations.That\'s not often the
reason in my experience. Pretty much all practical circuits are stiff, and
sim ok.

Very typical reasons for insanely short time steps are that the modal
derivative is discontinuous. The math algorithm thus simply fails.

\"If else\" type constructs will do this.

One should use functions such as

y = v(1).tanh(gain.v(test)) + v(2).(1-tanh(gain.(v(test))


to select between one voltage or the other smoothly with a continuous
derivative, gain sets how sharp the tanh \"switches\"

One need to make sure that there are no fast edges going directly into large
caps with no series resistor, resulting in extremely large currents. Put a
resistor across inductors. All switching edges should be RC filtered.

There is a list of dos and don\'t such as only span 12 orders for resistance,

The problem is that, and lets face the reality, most \"pro\" model makers
don\'t know diddly squat about them....

The design of a good model is as hard as a good analog circuit design is.
There aren\'t many good analog designers....

Model making requires some knowledge of how spice calculates to avoid the
obvious problems.

I haven\'t looked at the model in question, but I do know that I have a basic
functional current mode controller (CurrentModeController.sss) in SuperSpice
running in around 5 secs, thus I find it difficult to hold that some more
advanced controller model has to take many hours to run.

One of longest running examples in SuperSpice is SuperHetRadioFrontEnd.sss.
It takes 2 minutes on my laptop which does around 90 GFlops.

For those of you that know about 60s/70s 6 transistor radios.

It has an AM input driving an oscillating mixer into 3 stages of IF at
455Khz to its demodulated output.

The \"stiff\" nature of the circuit in that it needs to have the 1 MHz running
many cycles and deal with the LF modulation.

Kevin Aylward

https://www.kevinaylward.co.uk/gr/index.html
http://www.anasoft.co.uk/ SuperSpice - Freeware - complete
http://www.kevinaylward.co.uk/ee/index.html

 

[Kevin Aylward]

\"Phil Hobbs\" wrote in message
news:4f5595a2-ab59-a6d9-ee64-a4eb8835295a@electrooptical.net...

Joe Gwinn wrote:

On Tue, 25 Oct 2022 07:56:38 -0700, John Larkin

The guy running this for me has a pretty good, fairly new PC. But the
sim takes hours to simulate 10s of milliseconds, so we don\'t want a
modest speedup.

TI software, TI models, runs for hours. That\'s silly.

My recollection from my power-system colleagues is that this can be
caused by often parasitic sub circuits with very short time constants
(compared to the core circuit), so the approach was to model only the
core circuit at first, then start to decorate it.

Joe Gwinn

The Gear integrator is specifically designed for problems like that.
(\"stiff systems\").

Cheers

Phil Hobbs

Well... ......

I have truly run millions of sims.......so..... (Cadence, ASIC design, not
SuperSpice)

Gear v Trap in practice really don\'t have much between them in terms of
speed or convergence statistically.

I might use trap when there is the characteristic triangular numerical
error. Generally always use trap for oscillators to avoid correct damping.

The main determiner of simulation time for a given circuit is reltol, tratol
max, step time.

If these are not set \"appropriately\", results can be totally garbled.

The Spice3 default for tratol is 7. To ensure that off the bat, SMPS sim
correctly trtol needs to be set to 1, however trtol=7 can run 3 times as
fast as trtol=1.

Tests need to be done on the circuit to see if intermediate values can be
reliably used.


The fundamental problem in these models is generally complete le lack of
model design knowledge.

A model needs to be designed just as a real circuit. On has to know what
causes slowdowns due to convergence problems.

Kevin Aylward

https://www.kevinaylward.co.uk/gr/index.html
http://www.anasoft.co.uk/ SuperSpice Freeware
http://www.kevinaylward.co.uk/ee/index.html

 

[Joe Gwinn]

On Thu, 27 Oct 2022 08:09:08 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

On Thu, 27 Oct 2022 13:46:47 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 20:29, Phil Hobbs wrote:
John Larkin wrote:
On Wed, 26 Oct 2022 08:56:04 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a
bit of
spurious dissipation 1M to ground here and there might take the
edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

If we can\'t reasonably sim it, we\'ll build it. I can imagine the three
secondary switchers, negative impedance loads, making the first one
oscillate. That\'s not a risk we want on our new delay generator.

Each reg needs output caps of unknown value, and feedforward caps in
its fedback divider. May as well get all that right.

What might break the deadlock for computation is add a small series
resistance to the capacitance after the first regulator to low pass
filter it. The trick will be to find something modest enough to not
affect the predictions much but sufficient to compute it more easily.

You might have to do something like that IRL too.

I expect they never expected you to daisy chain them back to back like
that and the output of the first one really doesn\'t like facing the
negative impedance dynamic load. Classic way to make an oscillator.

Parasitic things with ridiculously high Q can ring if provoked which is
why adding the odd spurious dissipative resistor to certain key nodes
sometimes helps instil good behaviour. Jeroen has made the same point.

I wish TI knew all that.


I suspect they give their modelers tight budgets for how many hours they
can spend per model.

And that they never considered the output of one driving the inputs of
several others.

Here\'s what I have so far. The first switcher sees a complex load,
some of which is negative impedance. We\'ll split the board into noisy
and quiet \"Q\" halves with ferrite beads bridging the power pours. That
makes the impedances yet more interesting.

https://www.dropbox.com/s/pklyt3mrlvf3ewm/28S662A7_power.pdf?dl=0

I hope it\'s not that ratty in real life, and is somewhat more
efficient.

The power-supply guys I knew had no problem getting cascaded switchers
(and linear final regulators) to work. They simulated the whole
combined assembly of voltage regulators, and paid a lot of attention
to loop filters and cascade filters. Not to mention cables between,
if present. The whole circuit. All this being simulated using
LTspice, but with proprietary locally developed models.

This being 2022, the design is dominated by what we can get.

We have managed to get the TI switchers to work in LT Spice at
bearable speeds, tens of minutes per run instead of overnight. I don\'t
trust the results, especially for the first switcher, the TPS54302.

https://www.dropbox.com/s/sd5640vv8et0jb1/TPS54302_Sim_JL1.jpg?raw=1

The sim log file is full of complaints about bad curly brackets and
such. I didn\'t draw any curly brackets.

Switchers driving switchers is common. Nobody likes going from 24
volts to 1 volt, even if you can get the parts.

Go to the TI or ADI web site and look at New Products. It\'s mind
boggling. How can they support, and make good models for, all those
parts? How long will they keep making them?

By extensive cut-and-paste reuse?

Joe Gwinn

 

[Phil Hobbs]

Kevin Aylward wrote:

\"Phil Hobbs\"  wrote in message
news:4f5595a2-ab59-a6d9-ee64-a4eb8835295a@electrooptical.net...

Joe Gwinn wrote:
On Tue, 25 Oct 2022 07:56:38 -0700, John Larkin

The guy running this for me has a pretty good, fairly new PC. But the
sim takes hours to simulate 10s of milliseconds, so we don\'t want a
modest speedup.

TI software, TI models, runs for hours. That\'s silly.

My recollection from my power-system colleagues is that this can be
caused by often parasitic sub circuits with very short time constants
(compared to the core circuit), so the approach was to model only the
core circuit at first, then start to decorate it.

Joe Gwinn

The Gear integrator is specifically designed for problems like that.
(\"stiff systems\").

Cheers

Phil Hobbs

Well... ......

I have truly run millions of sims.......so..... (Cadence, ASIC design,
not SuperSpice)

Gear v Trap in practice really don\'t have much between them in terms of
speed or convergence statistically.

Stiff systems are only one variety of ill-conditioned simulations, sure.
As the wise man said, \"you can\'t make anything foolproof because fools
are so ingenious.\"

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[John Larkin]

On Thu, 27 Oct 2022 20:02:03 +0100, \"Kevin Aylward\"
<kevinRemoveandReplaceATkevinaylward.co.uk> wrote:

\"Martin Brown\" wrote in message news:tjap6l$4vg$1@gioia.aioe.org...

On 26/10/2022 04:41, John Larkin wrote:
On Tue, 25 Oct 2022 21:52:46 +0100, Martin Brown
\'\'\'newspam\'\'\'@nonad.co.uk> wrote:


Chances are one or more of the equations is stiff and the time step is
becoming infinitessimal on one of the rapid transitions. Adding a bit of
spurious dissipation 1M to ground here and there might take the edge off
whatever is making it so stiff.

We are running TI\'s Cadence sim and TI\'s encrypted switcher chip
models.

We just discovered that their TPS562208 model runs about 50x faster
than the TPS54302 model. They are very similar chips. We have both in
our power supply design, one 54302 pre-regulating for three of the
562208\'s.

It might be worth building one to see if it really is inclined to squeg
in real circuits. The sim could be telling you something important.

Yes. We just decided to do a quick-turn 4-layer board with all four
switchers. TI\'s spice models are insane and admittedly don\'t fully
model the devices.

I just need a 12 volt 9 tera-amp bench supply to run it.

https://www.dropbox.com/s/sd5640vv8et0jb1/TPS54302_Sim_JL1.jpg?raw=1

 

[Jan Panteltje]

On a sunny day (Thu, 27 Oct 2022 09:33:12 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<99cllhp645bv1v1qsk0hb2nccifpbecgvn@4ax.com>:

I am struggling for every square mm of board area.

OTOH BAD things must happen for those parts not to be around anymore

Parts seem to be available more lately, especially direct from TI.




That was to keep my drone airborne via a thin coax carrying high voltage
transformed back to 7V at the drone:
http://panteltje.com/pub/drone_power_small_core_test_IMG_6114.JPG
http://panteltje.com/pub/h501s_drone_remote_power_flight_test_1_IMG_6274.JPG
http://panteltje.com/pub/h501s_drone_remote_power_test_ground_control_1_IMG_6276.JPG

I tested a 30 ga twisted pair of magnet wire. It failed at 1400 volts.
Wire-wrap wire must be 10 KV-ish. You\'d need a clever HV downconverter
to use really light wire.

How about a single wire to power a drone?

How would that work?
Maybe optical fiber for a high power laser? Never tried that, do have some optical fiber here..
These coaxes I use have teflon based insulation and are really good for some hundreds of volts,
very light at that,
The idea was to make as little RF as possible (am using about 100 kHz), put a small antenna on the drone
and send the amplified received RF down the same coax (many MHz), or even use the whole coax
as shortwave antenna, balloon would work too of course,
just playing and investigating