ERROR: Reference to vector reg 'InKbWd' is not a legal net l

A

Aldorus

Guest
Hello:


I am trying to implement a PS2 keyboard read routine. Basically,
use the keyboard clock to shift 11 bits through a register. I am getting
an odd error. Heres a SMALL snippet that shows the error under ISE 9


*******************************************
module _kb_echo (input ExtClk,
input ExtRst,
input ExtKbClk,
input ExtKbData,
output [1:0] ExtLedVcc,
output [6:0] ExtLedC);


reg [10:0] InKbWd;

mod_kb_read _mod_kb_read(ExtRst,ExtKbClk,ExtKbData,InKbWd);

endmodule


module mod_kb_read (input Rst,
input KbClk,
input KbData,
output reg [10:0] KbWd);

always @ (negedge KbClk or negedge Rst)
begin
KbWd[0] <= KbData;
KbWd[1] <= KbWd[0];
KbWd[2] <= KbWd[1];
KbWd[3] <= KbWd[2];
KbWd[4] <= KbWd[3];
KbWd[5] <= KbWd[4];
KbWd[6] <= KbWd[5];
KbWd[7] <= KbWd[6];
KbWd[8] <= KbWd[7];
KbWd[9] <= KbWd[8];
KbWd[10] <= KbWd[9];
end
endmodule



***********************************************
Heres the offending line:
reg [10:0] InKbWd;
mod_kb_read _mod_kb_read(ExtRst,ExtKbClk,ExtKbData,InKbWd); <---

Why would it complain about an 11 bit register?

Thanks
 
On 3/17/2011 2:52 PM, Aldorus wrote:

I am trying to implement a PS2 keyboard read routine. Basically,
use the keyboard clock to shift 11 bits through a register. I am getting
an odd error. Heres a SMALL snippet that shows the error under ISE 9
Click to expand...
Actually that's a perfectly acceptable, though sparse, message when you
incorrectly connect a module output to a register.

The InKbWd signal should be declared as a wire (net) instead of a reg
(variable).

Cary
 
On Thu, 17 Mar 2011 21:52:50 GMT, Aldorus wrote:

*******************************************
module _kb_echo (yada yada);

reg [10:0] InKbWd;

mod_kb_read _mod_kb_read(ExtRst,ExtKbClk,ExtKbData,InKbWd);

endmodule

module mod_kb_read (input Rst,
input KbClk,
input KbData,
output reg [10:0] KbWd);
snip
***********************************************
Heres the offending line:
reg [10:0] InKbWd;
mod_kb_read _mod_kb_read(ExtRst,ExtKbClk,ExtKbData,InKbWd); <---

Why would it complain about an 11 bit register?
Click to expand...
Because you've connected the output of a module
instance (instance _mod_kb_read of module mod_kb_read)
to a variable (reg [10:0] InKbWd).

Within the module mod_kb_rd you have used the variable
KbWd quite correctly, writing to it from procedural
code in the always block. No need to change any of that.

Outside the module, the instance's output port acts as
a continuous driver on whatever you connect to that
output port. Consequently, that connection must be
a net (i.e. a "wire [10:0]" in your case). Simply
re-declare InKbWd as wire[10:0] and all will be well.

This rule, which appears somewhat strange at first
glance but actually makes quite a lot of sense, is
much relaxed in SystemVerilog and therefore your
original code should be accepted by your tools if
you flip the necessary command-line switches.
However, some of the low-end and FPGA tools
haven't yet caught up with this, so it's still
a good plan to follow the traditional Verilog
rules...
- If a Thing is given its value by procedural
assignment, then that Thing must be a variable
(reg, integer or one of a few other types).
- If a Thing is given its value by any other
means - in particular, by being driven from
something on the other side of a port boundary,
or driven by a continuous assignment - then
the Thing must be a net (wire).

"Continuous assignment" means the assign
statement appearing at the top level of
a module: assign some_net = some_expression;
Not to be confused with procedural continuous
assignment - the assign keyword appearing in
procedural code - which you would do well to
avoid like the plague.
--
Jonathan Bromley
 
Thanks guys. I have to go re-read the section on wire/net and reg/int.
This assignment rules have me confused
 
aldorus <him@here.com> wrote:

Thanks guys. I have to go re-read the section on wire/net and reg/int.
This assignment rules have me confused
Click to expand...
It confused me a while in the beginning. I mostly write strutural
verilog (modules and continuous assign) but FFs only work in
behavioral verilog.

The way I think about it is that reg keeps its value, like with
a capacitor (in the days of dynamic logic), or a keeper (now).
That allows the behavioral assignment to work, such that the
value stays between asssignments. A wire must always have
a driver (unless it allows for tristate).

-- glen
 
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