T
Trit
Guest
I'm relatively inexperienced with VHDL but am doing a project
involving it. I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.
The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form <= "value"
Example (first two errors in compile) of the relevant code
Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
..
..
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
..
..
30: case waitbit_state is
31: -- wait state
32: when "00"=>
33: if(waitbit_start = '0') then waitbit_nextstate <= "00",
waitbit_end <= '0';
34: else waitbit_nextstate <= "01", waitbit_end <= '0';
35: end if;
error output is
** Error: E:/project...(33): Type error resolving infix expression
"<=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"<=" as type ieee.std_logic_1163.std_logic_vector.
and a few more of the same for the other occurances in the state
machine
Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this? I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?
involving it. I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.
The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form <= "value"
Example (first two errors in compile) of the relevant code
Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
..
..
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
..
..
30: case waitbit_state is
31: -- wait state
32: when "00"=>
33: if(waitbit_start = '0') then waitbit_nextstate <= "00",
waitbit_end <= '0';
34: else waitbit_nextstate <= "01", waitbit_end <= '0';
35: end if;
error output is
** Error: E:/project...(33): Type error resolving infix expression
"<=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"<=" as type ieee.std_logic_1163.std_logic_vector.
and a few more of the same for the other occurances in the state
machine
Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this? I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?