ERROR: infix expression "<=" with simple vectors

T

Trit

Guest
I'm relatively inexperienced with VHDL but am doing a project
involving it. I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.

The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form &lt;= "value"

Example (first two errors in compile) of the relevant code

Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
..
..
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
..
..

30: case waitbit_state is
31: -- wait state
32: when "00"=&gt;
33: if(waitbit_start = '0') then waitbit_nextstate &lt;= "00",
waitbit_end &lt;= '0';
34: else waitbit_nextstate &lt;= "01", waitbit_end &lt;= '0';
35: end if;

error output is

** Error: E:/project...(33): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.

and a few more of the same for the other occurances in the state
machine

Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this? I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?
 
Trit,
You should copy Jeff's code as he corrected your
issue without seeing it. You had a "," in a place
where you needed a ";".

Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis SynthWorks VHDL Training http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.
 
On Feb 23, 9:56 am, Trit &lt;tritous_cara...@hotmail.com&gt; wrote:
I'm relatively inexperienced with VHDL but am doing a project
involving it.  I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.

The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form &lt;= "value"

Example (first two errors in compile) of the relevant code

Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
.
.
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
.
.

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then waitbit_nextstate &lt;= "00",
waitbit_end &lt;= '0';
34:             else waitbit_nextstate &lt;= "01", waitbit_end &lt;= '0';
35:             end if;

error output is

** Error: E:/project...(33): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.

and a few more of the same for the other occurances in the state
machine

Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this?  I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?
Click to expand...
You could try writing it like this:

30: case waitbit_state is
31: -- wait state
32: when "00"=&gt;
33: if(waitbit_start = '0') then
33a: waitbit_nextstate &lt;= "00";
33b: waitbit_end &lt;= '0';
34: else
34a: waitbit_nextstate &lt;= "01";
34b: waitbit_end &lt;= '0';
35: end if;
 
On Feb 23, 10:34 am, nuckols.j...@gmail.com wrote:
On Feb 23, 9:56 am, Trit &lt;tritous_cara...@hotmail.com&gt; wrote:





I'm relatively inexperienced with VHDL but am doing a project
involving it.  I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.

The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form &lt;= "value"

Example (first two errors in compile) of the relevant code

Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
.
.
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
.
.

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then waitbit_nextstate &lt;= "00",
waitbit_end &lt;= '0';
34:             else waitbit_nextstate &lt;= "01", waitbit_end &lt;= '0';
35:             end if;

error output is

** Error: E:/project...(33): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.

and a few more of the same for the other occurances in the state
machine

Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this?  I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?

You could try writing it like this:

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then
33a:                waitbit_nextstate   &lt;= "00";
33b:                waitbit_end         &lt;= '0';
34:             else
34a:               waitbit_nextstate    &lt;= "01";
34b:               waitbit_end          &lt;= '0';
35:             end if;- Hide quoted text -

- Show quoted text -
Click to expand...
Whoops! Now I see the problem. The vectors are 3 bits (2 downto 0) and
you've assigned only 2 bits ("00" and "01"). Maybe you really want
"000" and "001".
 
On 23 Feb, 15:34, nuckols.j...@gmail.com wrote:
On Feb 23, 9:56 am, Trit &lt;tritous_cara...@hotmail.com&gt; wrote:





I'm relatively inexperienced with VHDL but am doing a project
involving it.  I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.

The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form &lt;= "value"

Example (first two errors in compile) of the relevant code

Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
.
.
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
.
.

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then waitbit_nextstate &lt;= "00",
waitbit_end &lt;= '0';
34:             else waitbit_nextstate &lt;= "01", waitbit_end &lt;= '0';
35:             end if;

error output is

** Error: E:/project...(33): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.

and a few more of the same for the other occurances in the state
machine

Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this?  I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?

You could try writing it like this:

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then
33a:                waitbit_nextstate   &lt;= "00";
33b:                waitbit_end         &lt;= '0';
34:             else
34a:               waitbit_nextstate    &lt;= "01";
34b:               waitbit_end          &lt;= '0';
35:             end if;- Hide quoted text -

- Show quoted text -
Click to expand...
I did originally try this and it didn't work (probably forgot to save
before compiling, stare at code enough and that happens).

Splitting the lines does seem to be working now, however, so thanks.
It was originally separated lines but it shifted to single line when I
changed editors. Guess I can focus on my typos now (much more fun).
 
On 23 Feb, 15:42, nuckols.j...@gmail.com wrote:
On Feb 23, 10:34 am, nuckols.j...@gmail.com wrote:





On Feb 23, 9:56 am, Trit &lt;tritous_cara...@hotmail.com&gt; wrote:

I'm relatively inexperienced with VHDL but am doing a project
involving it.  I'm currently systematically filtering out the usual
typos and rookie mistakes...but have a problem which I cant seem to
fix and would like some advice.

The problem is that the modelsim compiler doesnt seem to accept an
assignment of signals of type std_logic_vector using quote marks of
form &lt;= "value"

Example (first two errors in compile) of the relevant code

Library IEEE;
use IEEE.std_logic_1164.all;
use Ieee.std_logic_unsigned.all;
.
.
signal waitbit_state : std_logic_vector (2 downto 0);
signal waitbit_nextstate : std_logic_vector (2 downto 0);
.
.

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then waitbit_nextstate &lt;= "00",
waitbit_end &lt;= '0';
34:             else waitbit_nextstate &lt;= "01", waitbit_end &lt;= '0';
35:             end if;

error output is

** Error: E:/project...(33): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.
** Error: E:/project...(34): Type error resolving infix expression
"&lt;=" as type ieee.std_logic_1163.std_logic_vector.

and a few more of the same for the other occurances in the state
machine

Need it be said, not being able to assign like this is awkward in a
state machine, so does anyone know any ways to solve this?  I'm
assuming the issue is the "00" isn't being interpreted as a logic
vector but as a numeric form?

You could try writing it like this:

30:     case waitbit_state is
31:     -- wait state
32:     when "00"=
33:             if(waitbit_start = '0') then
33a:                waitbit_nextstate   &lt;= "00";
33b:                waitbit_end         &lt;= '0';
34:             else
34a:               waitbit_nextstate    &lt;= "01";
34b:               waitbit_end          &lt;= '0';
35:             end if;- Hide quoted text -

- Show quoted text -

Whoops! Now I see the problem. The vectors are 3 bits (2 downto 0) and
you've assigned only 2 bits ("00" and "01"). Maybe you really want
"000" and "001".- Hide quoted text -

- Show quoted text -
Click to expand...
yeah, that problem I corrected earlier. Bad day = disorganised heap
of files in various states of debugging. I've just spent 5 mins
putting them in order so I can be more systematic lol. I'll make sure
the version i end up with has that one fixed, (it's a pretty
distictive error anyway). Mostly I have to worry about else if -&gt;
elsif and missing underscores in signal names. Sorry about that
confusion.
 
May I recommend, as you are new to VHDL, that you stop using
std_logic_unsigned/arith/signed and instead use the package
ieee.numeric_std instead? (As it is an IEEE standard, the others are
not).
Getting into the habit now will save you grief on here later.
 
On 23 Feb, 16:17, Tricky &lt;Trickyh...@gmail.com&gt; wrote:
May I recommend, as you are new to VHDL, that you stop using
std_logic_unsigned/arith/signed and instead use the package
ieee.numeric_std instead?  (As it is an IEEE standard, the others are
not).
Getting into the habit now will save you grief on here later.
Click to expand...
Yeah, 99% of the time I don't need it and dont include it (especially
since I've seen the grief others have, and especially since the
libraries are defined per entity). There are just a few cases such as
counters where I need to add 1 and need the unsigned library, unless
there is a way to do a increment without it?
 
On Feb 23, 9:58 am, Trit &lt;tritous_cara...@hotmail.com&gt; wrote:
On 23 Feb, 16:17, Tricky &lt;Trickyh...@gmail.com&gt; wrote:

May I recommend, as you are new to VHDL, that you stop using
std_logic_unsigned/arith/signed and instead use the package
ieee.numeric_std instead?  (As it is an IEEE standard, the others are
not).
Getting into the habit now will save you grief on here later.

Yeah, 99% of the time I don't need it and dont include it (especially
since I've seen the grief others have, and especially since the
libraries are defined per entity).  There are just a few cases such as
counters where I need to add 1 and need the unsigned library, unless
there is a way to do a increment without it?
Click to expand...
Use numeric_std instead.

-a
 
On 23 Feb, 18:17, Andy Peters &lt;goo...@latke.net&gt; wrote:
On Feb 23, 9:58 am, Trit &lt;tritous_cara...@hotmail.com&gt; wrote:

On 23 Feb, 16:17, Tricky &lt;Trickyh...@gmail.com&gt; wrote:

May I recommend, as you are new to VHDL, that you stop using
std_logic_unsigned/arith/signed and instead use the package
ieee.numeric_std instead?  (As it is an IEEE standard, the others are
not).
Getting into the habit now will save you grief on here later.

Yeah, 99% of the time I don't need it and dont include it (especially
since I've seen the grief others have, and especially since the
libraries are defined per entity).  There are just a few cases such as
counters where I need to add 1 and need the unsigned library, unless
there is a way to do a increment without it?

Use numeric_std instead.

-a
Click to expand...
that will still allow simple assignment of type x &lt;= x + '1'; ?
convenient. I'll do that thanks

Cheers for the help all, finally managed to turn today around into a
productive session (after an appallingly disappointing weekend of
downloading useless applications) thanks to your advice
 
Trit wrote:
Use numeric_std instead.

-a

that will still allow simple assignment of type x &lt;= x + '1'; ?
convenient. I'll do that thanks

Cheers for the help all, finally managed to turn today around into a
productive session (after an appallingly disappointing weekend of
downloading useless applications) thanks to your advice
Click to expand...
With numeric_std, you must either use the type unsigned or
signed. Currently the addition you show x &lt;= x + '1'; is
not supported (next revision vhdl-2008 it is), however, fortunately
there is an easier way to do it. The following are supported:

signal x : unsigned (7 downto 0) ;
.. . .

x &lt;= x + 1 ;
x &lt;= x + "1" ; -- adding with a vector
x &lt;= x + (0 =&gt; '1') ; -- more complicated than you need

-- x &lt;= x + '1' ; -- not supported until vhdl-2008 support

For more help with the math packages, see my
paper titled, "VHDL Math Tricks of the Trade"
that is posted at:
http://www.synthworks.com/papers/index.htm

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis SynthWorks VHDL Training http://www.synthworks.com

A bird in the hand may be worth two in the bush,
but it sure makes it hard to type.
 
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