Emulating Open-Collector operation with TTL 74LS138......

[Fred Bloggs]

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:

On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.

John

 

[Ricky]

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:

On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

I think you mean the lack of absolute maximum ratings for the outputs, as I\'m sure they never expected anyone to think it would be safe to treat a totem pole output to be treated as an open collector.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

 

[Ricky]

On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs.. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.

I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.

It\'s been too many years since I\'ve looked at waveforms of LSTTL signals on a scope. When I was looking at TTL signals, people didn\'t understand impedance matching very widely. But things worked pretty well without terminations. It was later that higher clock rates were attempted and people finally figured out that the signals were not reaching the other end of the trace perfectly when there was more than one receiver. Also, CMOS.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

 

[whit3rd]

On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:

LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being
avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought
transmission line effects into standard logic design. If the typical LS output gate transitioned
a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...

Typical margins are factor of 2x or more, making a withstanding voltage of 20V
a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.

Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
There\'s certainly protection diodes built into its outputs (MOS body diode).
74ACT138 can take 50 mA into its output pin.

<https://www.ti.com/lit/ds/symlink/cd74act138.pdf>

 

[John Walliker]

On Saturday, 8 October 2022 at 05:07:50 UTC+1, whit3rd wrote:

On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:

LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being
avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought
transmission line effects into standard logic design. If the typical LS output gate transitioned
a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...
Typical margins are factor of 2x or more, making a withstanding voltage of 20V
a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
There\'s certainly protection diodes built into its outputs (MOS body diode).
74ACT138 can take 50 mA into its output pin.

https://www.ti.com/lit/ds/symlink/cd74act138.pdf

The problem with that is that the darlington would never turn off.

John

 

[John Walliker]

On Saturday, 8 October 2022 at 02:52:12 UTC+1, Ricky wrote:

On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.

It\'s been too many years since I\'ve looked at waveforms of LSTTL signals on a scope. When I was looking at TTL signals, people didn\'t understand impedance matching very widely. But things worked pretty well without terminations. It was later that higher clock rates were attempted and people finally figured out that the signals were not reaching the other end of the trace perfectly when there was more than one receiver. Also, CMOS.

It has been many years for me too. I spent several months in 1974 building
prototype digital television equipment using 74S devices. I don\'t recall ever
seeing overshoots of more than about 6V. I had access to excellent test equipment.
However, this was all hand-wired on perforated Veroboard and any signals going
more than a couple of cm were wired as twisted pair. Every chip usually had its own
decoupling capacitor, chosen for low Q so as to absorb switching transients..

John

 

[John Robertson]

On 2022/10/08 2:54 a.m., John Walliker wrote:

On Saturday, 8 October 2022 at 05:07:50 UTC+1, whit3rd wrote:
On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:

LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being
avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought
transmission line effects into standard logic design. If the typical LS output gate transitioned
a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...
Typical margins are factor of 2x or more, making a withstanding voltage of 20V
a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
There\'s certainly protection diodes built into its outputs (MOS body diode).
74ACT138 can take 50 mA into its output pin.

https://www.ti.com/lit/ds/symlink/cd74act138.pdf

The problem with that is that the darlington would never turn off.

John

Which is why we went back to the original 7445 device for this small run
(Rotation 8 pinball by Midway) replacement MPU board. The open-collector
was needed for allowing the TIP125 to turn off...we are going to make a
simple tiny sub-board to sub the 7445 in for the 138 and use a couple of
extra gates on the MPU to get the select logic right. The initial run
was five PCBs, the next run will have the fix built in of course.

Thanks for all the ideas folks - appreciate your efforts! Reworking
1970s tech can be fun!

John :-#)#
--
(Please post followups or tech inquiries to the USENET newsgroup)
John\'s Jukes Ltd.
MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3
(604)872-5757 (Pinballs, Jukes, Video Games)
www.flippers.com
\"Old pinballers never die, they just flip out.\"

 

[Fred Bloggs]

On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:

On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.

Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn\'t, and here\'s why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.

Stuff like shows why you\'re okay using unterminated lines most of the time for combinatorial inputs- it\'s the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they\'re good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It\'s only needed in extreme situations where the line has to be run over 18\" or so for some reason.

It\'s been too many years since I\'ve looked at waveforms of LSTTL signals on a scope. When I was looking at TTL signals, people didn\'t understand impedance matching very widely. But things worked pretty well without terminations. It was later that higher clock rates were attempted and people finally figured out that the signals were not reaching the other end of the trace perfectly when there was more than one receiver. Also, CMOS.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

 

[Phil Hobbs]

Fred Bloggs wrote:

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin
wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original
circuit.

He\'s just one of those people who, when they can\'t understand
something, think something is wrong. LS doesn\'t have ESD clamp
diodes on its outputs, and, in fact, nothing is being avalanched
by applying a very current limited 20V to its outputs. Maybe an
insignificant elevated leakage is all that happens. The original
circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does
depend on parameters that are not specified in the data sheet like
the breakdown voltage of the output pull-down transistor, so I
wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall
times of the logic family brought transmission line effects into
standard logic design.

Don\'t know that I\'ve ever seen \"LS TTL\" and \"ultrafast\" in the same
connection.

If the typical LS output gate transitioned a typical high impedance
interconnecting trace to 5V, and that 5V pulse meets a high
impedance input of another LS gate as its only load. The signal will
be reflected 100% positively for 5V traveling back down the trace to
the driver. Since the driver pulled high is high impedance, the
returning pulse again is reflected positively 100% making the voltage
at the driver output 10V.

In real life it\'s never that bad. LS doesn\'t drive heavy loads (i.e.
50-100 ohms) very fast in the positive direction, and the ~10 ns edges
mean that a normal-size board is too small to give that much
overshoot--the rise is still going on at the driver when the reflection
arrives.

The new +5V transition sends a 10V edge traveling down the line to
the LS input and gets clamped at 5V which is a full negative
reflection to return back to the driver and reduce the 10V at the
output node ideally to 5V etc. So we know for a *fact* the process
has to be designed to withstand a repetitive 10V applied to the
output.

Nah.

And that\'s not just withstand to survive, that\'s withstand with no
internal circuit disruption. Typical margins are factor of 2x or
more, making a withstanding voltage of 20V a done deal, and that can
be verified for the part. That\'s why I\'m saying it\'s a good design.

Your average NPN BE junction avalanches at about 6V, leading to
progressively reduced beta as well as current loading. The duty cycles
of the lights on that machine are probably less than 50%, so it\'ll be in
avalanche most of the time.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Phil Hobbs]

whit3rd wrote:

On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:

LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being
avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought
transmission line effects into standard logic design. If the typical LS output gate transitioned
a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...

Typical margins are factor of 2x or more, making a withstanding voltage of 20V
a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.

Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
There\'s certainly protection diodes built into its outputs (MOS body diode).
74ACT138 can take 50 mA into its output pin.

https://www.ti.com/lit/ds/symlink/cd74act138.pdf

The lights would be on continuously, looks like. Using HC plus cascode
FETs would be a complete solution, though.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Ricky]

On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:

On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\"..
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.
Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn\'t, and here\'s why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.

Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.


> Stuff like shows why you\'re okay using unterminated lines most of the time for combinatorial inputs- it\'s the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they\'re good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It\'s only needed in extreme situations where the line has to be run over 18\" or so for some reason.

Funny, I\'ve worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.

It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

 

[John Larkin]

On Fri, 7 Oct 2022 16:10:18 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal
circuit
disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.



John

LS has wussy pullups and is not very fast. LS is \"low power schottky\"
logic. Zs is around 100 ohms and rise is slow. It won\'t drive a
transmission line very hard.

See fig 25. Barely any reflection overshoot, certainly not over +5.

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwjvpfDVgtH6AhWuKUQIHUJMA6sQFnoECDoQAQ&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fsdya009&usg=AOvVaw2oKKkUlZ0b2DDwfOBBKOMt

So not \"for a *fact*\"

 

[John Larkin]

On Thu, 6 Oct 2022 08:29:16 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
controller.

Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
a 74LS138.

Trying to solve this without a driver transistor. The circuit is for a
1ms ~20V strobe pulse repeated every ten ms.

I thought of putting a 10ufd cap in series with R2, but don\'t like
electrolytics as they fail after a few thousand hours.

Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
that won\'t work reliably.

Anyone have a single component in mind that will essentially emulate
(isolate) an Open-Collector output for the 138?

The TIP125 is a complementary dual.

It\'s a single TO-220 PNP.

 

[Fred Bloggs]

On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:

On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.
Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn\'t, and here\'s why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
Stuff like shows why you\'re okay using unterminated lines most of the time for combinatorial inputs- it\'s the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they\'re good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It\'s only needed in extreme situations where the line has to be run over 18\" or so for some reason.
Funny, I\'ve worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.

What\'s funny is that you\'re so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.

It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.

The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

 

[John Larkin]

On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

Lasse Langwadt Christensen wrote:
torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
Lasse Langwadt Christensen wrote:
torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
John Robertson wrote:
On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
John Robertson wrote:
Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
controller.

Problem is of course, that R2 puts the ~20VDC to the TTL output gate
on a 74LS138.

Trying to solve this without a driver transistor. The circuit is for
a 1ms ~20V strobe pulse repeated every ten ms.

I thought of putting a 10ufd cap in series with R2, but don\'t like
electrolytics as they fail after a few thousand hours.

Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
so that won\'t work reliably.

Anyone have a single component in mind that will essentially emulate
(isolate) an Open-Collector output for the 138?

Thanks!

John :-#)#

Switch it to a 139 and use a 2N7002?

Cheers

Phil Hobbs


Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
drivers.

Circuit I am trying to fix with fewest components - one x two legged
device preferred per 138 output:

https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png

VLAMP is roughly 20VDC.

Thanks,

John :-#)#
The MOSFET cascode thing is pretty good actually, if you put a diode to
the supply or want to live dangerously and rely on the ESD protection to
discharge the gate. If it\'s a matter of using the boards or tossing
them, there\'s not much to lose by using barefoot FETs.


\'138 is push-pull, though very wimpy high side

Sure, but anything above +4ish reverse-biases the upper output transistor.
Cheers

with the upper transistor on does it ever get there?



Sure, it\'s an NPN emitter. If it were a NFET, it would be fine.

Cheers

Phil Hobbs

LS has a darlington with 110 ohms in the drain and probably no ESD
diode to +5.

It\'s shocking how poorly specified all those old TTL parts were.
Modern logic isn\'t much better. We have to measure stuff like Zout and
rise/fall times. Sometimes the results are startling.

We just yesterday decided that an efinix FPGA output was a pretty good
50 ohm source termination, so made the traces 50 ohms and deleted some
r-packs.

 

[Fred Bloggs]

On Saturday, October 8, 2022 at 12:49:44 PM UTC-4, John Larkin wrote:

On Fri, 7 Oct 2022 16:10:18 -0700 (PDT), Fred Bloggs
bloggs.fred...@gmail.com> wrote:

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".

Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal
circuit
disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.



John
LS has wussy pullups and is not very fast. LS is \"low power schottky\"
logic. Zs is around 100 ohms and rise is slow. It won\'t drive a
transmission line very hard.

See fig 25. Barely any reflection overshoot, certainly not over +5.

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwjvpfDVgtH6AhWuKUQIHUJMA6sQFnoECDoQAQ&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fsdya009&usg=AOvVaw2oKKkUlZ0b2DDwfOBBKOMt

So not \"for a *fact*\"

It\'s about the same speed as standard TTL but with 1/3 the power supply current draw. That used to be a big deal.

My description of overshoot was \"idealized\" to put it mildly.

 

[Lasse Langwadt Christensen]

lørdag den 8. oktober 2022 kl. 19.12.59 UTC+2 skrev Fred Bloggs:

On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.
Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn\'t, and here\'s why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
Stuff like shows why you\'re okay using unterminated lines most of the time for combinatorial inputs- it\'s the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they\'re good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It\'s only needed in extreme situations where the line has to be run over 18\" or so for some reason.
Funny, I\'ve worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
What\'s funny is that you\'re so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.

It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.
The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.

1 inch of trace is a few hundred picoseconds

 

[Fred Bloggs]

On Saturday, October 8, 2022 at 1:22:23 PM UTC-4, lang...@fonz.dk wrote:

lørdag den 8. oktober 2022 kl. 19.12.59 UTC+2 skrev Fred Bloggs:
On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.
Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn\'t, and here\'s why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
Stuff like shows why you\'re okay using unterminated lines most of the time for combinatorial inputs- it\'s the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they\'re good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It\'s only needed in extreme situations where the line has to be run over 18\" or so for some reason.
Funny, I\'ve worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
What\'s funny is that you\'re so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.

It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.
The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.
1 inch of trace is a few hundred picoseconds

I was surprised by it too, but that was the Motorola official recommendation.

 

[Lasse Langwadt Christensen]

lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:

On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
pcdhSpamM...@electrooptical.net> wrote:

Lasse Langwadt Christensen wrote:
torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
Lasse Langwadt Christensen wrote:
torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
John Robertson wrote:
On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
John Robertson wrote:
Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
controller.

Problem is of course, that R2 puts the ~20VDC to the TTL output gate
on a 74LS138.

Trying to solve this without a driver transistor. The circuit is for
a 1ms ~20V strobe pulse repeated every ten ms.

I thought of putting a 10ufd cap in series with R2, but don\'t like
electrolytics as they fail after a few thousand hours.

Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
so that won\'t work reliably.

Anyone have a single component in mind that will essentially emulate
(isolate) an Open-Collector output for the 138?

Thanks!

John :-#)#

Switch it to a 139 and use a 2N7002?

Cheers

Phil Hobbs


Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
drivers.

Circuit I am trying to fix with fewest components - one x two legged
device preferred per 138 output:

https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png

VLAMP is roughly 20VDC.

Thanks,

John :-#)#
The MOSFET cascode thing is pretty good actually, if you put a diode to
the supply or want to live dangerously and rely on the ESD protection to
discharge the gate. If it\'s a matter of using the boards or tossing
them, there\'s not much to lose by using barefoot FETs.


\'138 is push-pull, though very wimpy high side

Sure, but anything above +4ish reverse-biases the upper output transistor.
Cheers

with the upper transistor on does it ever get there?



Sure, it\'s an NPN emitter. If it were a NFET, it would be fine.

Cheers

Phil Hobbs

LS has a darlington with 110 ohms in the drain and probably no ESD
diode to +5.

It\'s shocking how poorly specified all those old TTL parts were.
Modern logic isn\'t much better. We have to measure stuff like Zout and
rise/fall times. Sometimes the results are startling.

it should be in the IBIS file

 

[Fred Bloggs]

On Saturday, October 8, 2022 at 1:22:23 PM UTC-4, lang...@fonz.dk wrote:

lørdag den 8. oktober 2022 kl. 19.12.59 UTC+2 skrev Fred Bloggs:
On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

snip gibberish
That\'s not clear. Got a schematic?

He\'s wasting his time, there\'s nothing wrong with the original circuit.

He\'s just one of those people who, when they can\'t understand something, think something is wrong.
LS doesn\'t have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn\'t be comfortable calling it \"well designed\".
Well I would and here\'s why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that\'s not just withstand to survive, that\'s withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That\'s why I\'m saying it\'s a good design.
I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the \"high impedance\" trace, does not pull up to 5V in the first place. The \"high impedance\" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there\'s no need to worry about over voltage from reflections.
Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn\'t, and here\'s why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
Stuff like shows why you\'re okay using unterminated lines most of the time for combinatorial inputs- it\'s the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they\'re good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It\'s only needed in extreme situations where the line has to be run over 18\" or so for some reason.
Funny, I\'ve worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
What\'s funny is that you\'re so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.

It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.
The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.
1 inch of trace is a few hundred picoseconds

Guess I should add that recommendation was for the DIP packaging for which lead inductance was significant. It may not apply to the surface mount package.