Driver to drive?

[josephkk]

On Sat, 10 Aug 2013 09:23:23 -0700, DecadentLinuxUserNumeroUno wrote:

On Sat, 10 Aug 2013 09:14:00 -0700, Joerg <invalid@invalid.invalid
wrote:

The devices (uC and such) to be connected would likely run in a slow USB
2.0 mode, they can't do 3.0. The data rates are very low and only the
round-trip response latency counts.


Then make the actual loop response circuit remain outside the PC, with
the probes, and make the USB part simply a monitoring and control
interface for the fast response, locally attached loop control circuits.

Pretty much making the PC no more than a KVM device, as it were.
which
is how this should be approached anyway.

I see some very fast, accurate devices attached and controlled by
slow,
*very old* GPIB interfaces all the time. Because they do not rely on
the GPIB bus being *in* the control loop. It is merely for the
monitoring, control, and oversight interface, and the slow port speed
does not affect the speed at which the device control processes its
received data stream(s).

I pretty much have to agree with this design approach. I have seen lots
of SCADA systems with some quite high performance devices controlled by
ascii protocols over TIA-485 bus communications. They worked correctly
because they decoupled reliable real time parts from reliable slow
stochastic processes.

?-)

 

[josephkk]

On Sat, 10 Aug 2013 12:32:15 -0700, Joerg wrote:

DecadentLinuxUserNumeroUno wrote:
On Sat, 10 Aug 2013 09:14:00 -0700, Joerg <invalid@invalid.invalid
wrote:

The devices (uC and such) to be connected would likely run in a slow
USB 2.0 mode, they can't do 3.0. The data rates are very low and only
the round-trip response latency counts.


Then make the actual loop response circuit remain outside the PC,
with
the probes, and make the USB part simply a monitoring and control
interface for the fast response, locally attached loop control
circuits.


Sure, that's the old-fashioned way. But the reason for posting my
question was to find out how far one can reassonably push USB latency.

Depends a lot on the maximum consequences of momentary upsets. You

design medical devices, you do know this issue well.

Pretty much making the PC no more than a KVM device, as it were.
which
is how this should be approached anyway.


Not necessarily. There is a surprising trend towards moving more and
more of the signal processing and interactive stuff into the PC.
Software-defined radios and so on. They aren't there yet but have come a
long way since the days when the PC was merely a glorified speaker and
display.

Primarily done by mediocre engineers. Just put all the heavy lifting on

the PC because it provides an easy to use, comfortable programming
interface (to mediocre engineers {and management}). With the low cost of
powerful ARM chips and such, the is no longer proper incentive for that
approach for better grade engineers.

I see some very fast, accurate devices attached and controlled by
slow,
*very old* GPIB interfaces all the time. Because they do not rely on
the GPIB bus being *in* the control loop. It is merely for the
monitoring, control, and oversight interface, and the slow port speed
does not affect the speed at which the device control processes its
received data stream(s).


That's how we did it in the 80's

Seriously, in the 90's we already did ultrasound machine designs where
the PC became an integral part of the engine. However, that went
directly via the PC bus and we re-wrote some parts of the OS kernel.

This time it should be USB because it makes us hardware-independent. The
NVidia avenue or similar custom designs would not be so great for us
because then some smaller netbooks would no longer be feasible.

Really? Netbooks make perfectly fine graphic terminals and web browsers.

?-)

 

[Joerg]

josephkk wrote:

On Sat, 10 Aug 2013 12:32:15 -0700, Joerg wrote:

DecadentLinuxUserNumeroUno wrote:
On Sat, 10 Aug 2013 09:14:00 -0700, Joerg <invalid@invalid.invalid
wrote:

The devices (uC and such) to be connected would likely run in a slow
USB 2.0 mode, they can't do 3.0. The data rates are very low and only
the round-trip response latency counts.

Then make the actual loop response circuit remain outside the PC,
with
the probes, and make the USB part simply a monitoring and control
interface for the fast response, locally attached loop control
circuits.


Sure, that's the old-fashioned way. But the reason for posting my
question was to find out how far one can reassonably push USB latency.

Depends a lot on the maximum consequences of momentary upsets. You
design medical devices, you do know this issue well.

If it stretches one in 50 response times to 5msec or misses it
completely it'll be ok. If it slips into a mode where they all take
5msec or more the system quits working.

Pretty much making the PC no more than a KVM device, as it were.
which
is how this should be approached anyway.


Not necessarily. There is a surprising trend towards moving more and
more of the signal processing and interactive stuff into the PC.
Software-defined radios and so on. They aren't there yet but have come a
long way since the days when the PC was merely a glorified speaker and
display.

Primarily done by mediocre engineers. Just put all the heavy lifting on
the PC because it provides an easy to use, comfortable programming
interface (to mediocre engineers {and management}). With the low cost of
powerful ARM chips and such, the is no longer proper incentive for that
approach for better grade engineers.

Nope. We did exactly that (using the PC as the realtime engine) in one
company. All cutting edge engineers, and an ARM would have been
hopelessly underpowered for the required image processing.

I see some very fast, accurate devices attached and controlled by
slow,
*very old* GPIB interfaces all the time. Because they do not rely on
the GPIB bus being *in* the control loop. It is merely for the
monitoring, control, and oversight interface, and the slow port speed
does not affect the speed at which the device control processes its
received data stream(s).

That's how we did it in the 80's

Seriously, in the 90's we already did ultrasound machine designs where
the PC became an integral part of the engine. However, that went
directly via the PC bus and we re-wrote some parts of the OS kernel.

This time it should be USB because it makes us hardware-independent. The
NVidia avenue or similar custom designs would not be so great for us
because then some smaller netbooks would no longer be feasible.

Really? Netbooks make perfectly fine graphic terminals and web browsers.

But you have no impact on what's in them. They do not have any PCI slots
to stick a custom card into.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[Jan Panteltje]

On a sunny day (Tue, 13 Aug 2013 22:08:50 -0700 (PDT)) it happened
eric@bauld.com wrote in
<30e3cc12-f9e9-49ab-a0b1-3b50757493d7@googlegroups.com>:

I have been all over the place and cannot seem to find an actual explanatio=
n for one or many possible solutions on the race state of a SR Latch on ini=
tialization/power up

I have a small circuit on a bread board using an SR Latch, the circuit func=
tions correctly once power is on and the SR latch has been manually used to=
set the desired initial state.

But, the race condition when the circuit is powered is very indeterminate a=
nd it bounces back and forth to which state wins. But I cannot seem to find=
an explanation as to how to set the initial state properly and then have i=
t function as normal.

I have tried a few methods on my own but none seem reliable enough. Am I mi=
ssing something as it seems like it should be quite simple, but I have not =
seen a solution I can apply on my board. Either I'm blind and its right in =
front of my face or somehow I have been unable to Google it. Found a LOT of=
sites explaining the race condition, but no solutions on how to "set" it.=


-E

Not sure what your problem is,
but if you for example use a 74HC74 fliflop as set reset,
you can keep the set (or reset) input active for some ms with an RC time
so it always powers up in the required state.

As to 'oscillations' and 'race conditons'.
I hope you no do use one of the flimsy solderless 'breadboards',
a few ns bad contact and or slow edges will trigger a fliflop many times.
So make sure you rise and fall times are within spec.

 

[Klaus Kragelund]

On Wednesday, August 14, 2013 10:05:11 AM UTC+2, DaveC wrote:

oem power supply, 31.5 vdc 1.5 A.



I want to change the output to 24 v.



There is one 8-pin IC, labeled:



230D1

PUICO



I don't see a datasheet anywhere for this. 



Any ideas?

The NCP1230:

http://www.onsemi.com/pub_link/Collateral/NCP1230-D.PDF

Cheers

Klaus

 

[panfilero]

Thanks for the advice, it sounds really good, one concern I have is that it's tied too much to their design software they sell, I'd hate to spend 4 days learning how to use a software package to design magnetics or power supplies, I really do like the hands on aspect of it

 

On Wednesday, August 14, 2013 9:43:54 AM UTC-7, Jim Thompson wrote:

On Wed, 14 Aug 2013 11:34:20 -0500, Tim Wescott

tim> wrote:



On Tue, 13 Aug 2013 22:08:50 -0700, eric wrote:



I have been all over the place and cannot seem to find an actual

explanation for one or many possible solutions on the race state of a SR

Latch on initialization/power up



I have a small circuit on a bread board using an SR Latch, the circuit

functions correctly once power is on and the SR latch has been manually

used to set the desired initial state.



But, the race condition when the circuit is powered is very

indeterminate and it bounces back and forth to which state wins. But I

cannot seem to find an explanation as to how to set the initial state

properly and then have it function as normal.



I have tried a few methods on my own but none seem reliable enough. Am I

missing something as it seems like it should be quite simple, but I have

not seen a solution I can apply on my board. Either I'm blind and its

right in front of my face or somehow I have been unable to Google it.

Found a LOT of sites explaining the race condition, but no solutions on

how to "set" it.



Flip flops come up in indeterminate states unless you do something

explicit to reset them, or as Jan suggested, to make one input come up

slower than the other.



Because a symmetrical flip-flop that happens to be half way between a 0

state and a 1 state is inherently indeterminate as to which direction its

going to go, you're pretty much doomed to this problem unless you do

something about it.



Use a good POR (power-on-reset) circuit that also copes with

brown-outs.

The problem is I don't know of any POR circuit examples handling a SR Latch. What I am trying to solve is the fact that on power up the state of the latch is indeterminate. I know what I want it to be but don't know how to ensure it starts in that state.

Or how would one make the input come up slower than the other? Bridge a capacitor on one side?
I am doing this on a solder less bread board, but will be moving it to a protoboard once everything is figured out.

I have been doomed to the indeterminate problem but I don't have the knowledge or exp to know what solution is effective or "correct"

 

On Wednesday, August 14, 2013 11:33:24 AM UTC-7, Jim Thompson wrote:

On Wed, 14 Aug 2013 13:12:03 -0500, Tim Wescott

tim@seemywebsite.really> wrote:



On Wed, 14 Aug 2013 09:43:54 -0700, Jim Thompson wrote:



On Wed, 14 Aug 2013 11:34:20 -0500, Tim Wescott

tim@seemywebsite.really> wrote:



On Tue, 13 Aug 2013 22:08:50 -0700, eric wrote:



I have been all over the place and cannot seem to find an actual

explanation for one or many possible solutions on the race state of a

SR Latch on initialization/power up



I have a small circuit on a bread board using an SR Latch, the circuit

functions correctly once power is on and the SR latch has been

manually used to set the desired initial state.



But, the race condition when the circuit is powered is very

indeterminate and it bounces back and forth to which state wins. But I

cannot seem to find an explanation as to how to set the initial state

properly and then have it function as normal.



I have tried a few methods on my own but none seem reliable enough. Am

I missing something as it seems like it should be quite simple, but I

have not seen a solution I can apply on my board. Either I'm blind and

its right in front of my face or somehow I have been unable to Google

it. Found a LOT of sites explaining the race condition, but no

solutions on how to "set" it.



Flip flops come up in indeterminate states unless you do something

explicit to reset them, or as Jan suggested, to make one input come up

slower than the other.



Because a symmetrical flip-flop that happens to be half way between a 0

state and a 1 state is inherently indeterminate as to which direction

its going to go, you're pretty much doomed to this problem unless you do

something about it.



Use a good POR (power-on-reset) circuit that also copes with brown-outs.



...Jim Thompson



Yup.



Virtually every chip I've designed in recent years has a complex POR.

A recent chip monitors three separate supplies for value and

sequencing before allowing the logic to fire up.



...Jim Thompson

--

| James E.Thompson | mens |

| Analog Innovations | et |

| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |

| San Tan Valley, AZ 85142 Skype: Contacts Only | |

| Voice480)460-2350 Fax: Available upon request | Brass Rat |

| E-mail Icon at http://www.analog-innovations.com | 1962 |



I love to cook with wine. Sometimes I even put it in the food.

Im using
http://www.digikey.ca/product-search/en?x=-1421&y=-72&lang=en&site=ca&KeyWords=HCF4001B
For a chip and using two of the NOR gates to build a Latch
http://upload.wikimedia.org/wikipedia/commons/a/a8/SR-NOR-latch.png

I have 13.5v powering the chip.
But I still don't follow how I can get this latch to power up in a specific state. Every time I restart it is seemingly random which side of the latch starts active.

Im not a EE, just a software guy trying that has really wanted to learn how to build electronics and is getting stuck.

 

[RobertMacy]

On Wed, 14 Aug 2013 08:03:33 -0700, panfilero <panfilero@gmail.com> wrote:

Thanks for the advice, it sounds really good, one concern I have is that
it's tied too much to their design software they sell, I'd hate to spend
4 days learning how to use a software package to design magnetics or
power supplies, I really do like the hands on aspect of it

Check out LTspice. It's free, educational, and has lots of support people.

 

On Wednesday, August 14, 2013 12:15:54 PM UTC-7, Tim Wescott wrote:

On Wed, 14 Aug 2013 11:49:42 -0700, eric wrote:



On Wednesday, August 14, 2013 11:33:24 AM UTC-7, Jim Thompson wrote:

On Wed, 14 Aug 2013 13:12:03 -0500, Tim Wescott



tim@seemywebsite.really> wrote:







On Wed, 14 Aug 2013 09:43:54 -0700, Jim Thompson wrote:







On Wed, 14 Aug 2013 11:34:20 -0500, Tim Wescott



tim@seemywebsite.really> wrote:







On Tue, 13 Aug 2013 22:08:50 -0700, eric wrote:







I have been all over the place and cannot seem to find an actual



explanation for one or many possible solutions on the race state

of a



SR Latch on initialization/power up







I have a small circuit on a bread board using an SR Latch, the

circuit



functions correctly once power is on and the SR latch has been



manually used to set the desired initial state.







But, the race condition when the circuit is powered is very



indeterminate and it bounces back and forth to which state wins.

But I



cannot seem to find an explanation as to how to set the initial

state



properly and then have it function as normal.







I have tried a few methods on my own but none seem reliable

enough. Am



I missing something as it seems like it should be quite simple,

but I



have not seen a solution I can apply on my board. Either I'm blind

and



its right in front of my face or somehow I have been unable to

Google



it. Found a LOT of sites explaining the race condition, but no



solutions on how to "set" it.







Flip flops come up in indeterminate states unless you do something



explicit to reset them, or as Jan suggested, to make one input come

up



slower than the other.







Because a symmetrical flip-flop that happens to be half way between

a 0



state and a 1 state is inherently indeterminate as to which

direction



its going to go, you're pretty much doomed to this problem unless

you do



something about it.







Use a good POR (power-on-reset) circuit that also copes with

brown-outs.







...Jim Thompson







Yup.







Virtually every chip I've designed in recent years has a complex POR.



A recent chip monitors three separate supplies for value and



sequencing before allowing the logic to fire up.







...Jim Thompson



--



| James E.Thompson | mens |



| Analog Innovations | et |



| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |



| San Tan Valley, AZ 85142 Skype: Contacts Only | |



| Voice480)460-2350 Fax: Available upon request | Brass Rat |



| E-mail Icon at http://www.analog-innovations.com | 1962 |







I love to cook with wine. Sometimes I even put it in the food.



Im using

http://www.digikey.ca/product-search/en?

x=-1421&y=-72&lang=en&site=ca&KeyWords=HCF4001B

For a chip and using two of the NOR gates to build a Latch

http://upload.wikimedia.org/wikipedia/commons/a/a8/SR-NOR-latch.png



I have 13.5v powering the chip.

But I still don't follow how I can get this latch to power up in a

specific state. Every time I restart it is seemingly random which side

of the latch starts active.



Yes. That is typical, and is to be expected unless you do something

special to make it not happen.



Im not a EE, just a software guy trying that has really wanted to learn

how to build electronics and is getting stuck.



Getting unstuck will teach you a lot, though!



You've been given answers, but maybe not ones that are "unwound" enough

to see them.



Since you're using NOR gates, I assume that your rest state has both

inputs to the SR latch high. What you need to do is to make sure that on

power-on, the correct input on each latch is held low long enough for the

latch to assume your desired state.



One way to do that is what Jan recommended: you make sure that on power-

up, one input always rises significantly slower than the other -- that

input will force its corresponding output to be high when things have

settled out.



Another way to do this is with an explicit reset circuit. You have a

circuit that detects when the power supply is below some threshold, and

as long as it is low, you hold selected inputs on your latches low. This

is easier to understand at a glance of the schematic, and more reliable,

but it takes more components.



I hope this makes sense -- if it doesn't, ask.



--



Tim Wescott

Wescott Design Services

http://www.wescottdesign.com

Thanks, I have learnt a lot already trying to figure this out. This is my first dip into IC's and circuit based logic. And really feel I have made progress, esp in understanding how little I know

I think my inexperience is culprit in not understanding the solutions presented. And I appreciate the help.

Now the power on state of the latch will have either R = 0 & S = 0
Or R=1 & S = 0, The problem is when when R = S = 0 and then the latch jumps into its race condition.

Not sure how a power on reset would work here, but I can understand putting a delay in between Q and S would yield the result I am looking for. And I would hope that it will initialize the latch with 'Q as high R=S=0.

Now, would a recommended method of doing this would be to put a capacitor on the Q,S link and ground. Would this slow down the race condition enough to allow the latch to initialize in the state I wish? Or is there another expected method used to cause this slow down?

For the explicit reset circuit, if one loses power. Regains power and once you are above the threshold and have proper power. How would the reset circuit integrate with the inputs on the latches, would it just trigger transistors on the RS inputs? Or would it have them in the way of the QS and 'QR pathways?
Because if its simply Preventing the input on the RS side, won't I have the same race condition of the RS latch being R=S=0 and then one side "winning" the race condition.

- E

 

On Wednesday, August 14, 2013 12:36:53 PM UTC-7, er...@bauld.com wrote:

On Wednesday, August 14, 2013 12:15:54 PM UTC-7, Tim Wescott wrote:

On Wed, 14 Aug 2013 11:49:42 -0700, eric wrote:







On Wednesday, August 14, 2013 11:33:24 AM UTC-7, Jim Thompson wrote:



On Wed, 14 Aug 2013 13:12:03 -0500, Tim Wescott







tim@seemywebsite.really> wrote:















On Wed, 14 Aug 2013 09:43:54 -0700, Jim Thompson wrote:















On Wed, 14 Aug 2013 11:34:20 -0500, Tim Wescott







tim@seemywebsite.really> wrote:















On Tue, 13 Aug 2013 22:08:50 -0700, eric wrote:















I have been all over the place and cannot seem to find an actual







explanation for one or many possible solutions on the race state



of a







SR Latch on initialization/power up















I have a small circuit on a bread board using an SR Latch, the



circuit







functions correctly once power is on and the SR latch has been







manually used to set the desired initial state.















But, the race condition when the circuit is powered is very







indeterminate and it bounces back and forth to which state wins..



But I







cannot seem to find an explanation as to how to set the initial



state







properly and then have it function as normal.















I have tried a few methods on my own but none seem reliable



enough. Am







I missing something as it seems like it should be quite simple,



but I







have not seen a solution I can apply on my board. Either I'm blind



and







its right in front of my face or somehow I have been unable to



Google







it. Found a LOT of sites explaining the race condition, but no







solutions on how to "set" it.















Flip flops come up in indeterminate states unless you do something







explicit to reset them, or as Jan suggested, to make one input come



up







slower than the other.















Because a symmetrical flip-flop that happens to be half way between



a 0







state and a 1 state is inherently indeterminate as to which



direction







its going to go, you're pretty much doomed to this problem unless



you do







something about it.















Use a good POR (power-on-reset) circuit that also copes with



brown-outs.















...Jim Thompson















Yup.















Virtually every chip I've designed in recent years has a complex POR..







A recent chip monitors three separate supplies for value and







sequencing before allowing the logic to fire up.















...Jim Thompson







--







| James E.Thompson | mens |







| Analog Innovations | et |







| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |







| San Tan Valley, AZ 85142 Skype: Contacts Only | |







| Voice480)460-2350 Fax: Available upon request | Brass Rat |







| E-mail Icon at http://www.analog-innovations.com | 1962 |















I love to cook with wine. Sometimes I even put it in the food.







Im using



http://www.digikey.ca/product-search/en?



x=-1421&y=-72&lang=en&site=ca&KeyWords=HCF4001B



For a chip and using two of the NOR gates to build a Latch



http://upload.wikimedia.org/wikipedia/commons/a/a8/SR-NOR-latch.png







I have 13.5v powering the chip.



But I still don't follow how I can get this latch to power up in a



specific state. Every time I restart it is seemingly random which side



of the latch starts active.







Yes. That is typical, and is to be expected unless you do something



special to make it not happen.







Im not a EE, just a software guy trying that has really wanted to learn



how to build electronics and is getting stuck.







Getting unstuck will teach you a lot, though!







You've been given answers, but maybe not ones that are "unwound" enough



to see them.







Since you're using NOR gates, I assume that your rest state has both



inputs to the SR latch high. What you need to do is to make sure that on



power-on, the correct input on each latch is held low long enough for the



latch to assume your desired state.







One way to do that is what Jan recommended: you make sure that on power-



up, one input always rises significantly slower than the other -- that



input will force its corresponding output to be high when things have



settled out.







Another way to do this is with an explicit reset circuit. You have a



circuit that detects when the power supply is below some threshold, and



as long as it is low, you hold selected inputs on your latches low. This



is easier to understand at a glance of the schematic, and more reliable,



but it takes more components.







I hope this makes sense -- if it doesn't, ask.







--







Tim Wescott



Wescott Design Services



http://www.wescottdesign.com



Thanks, I have learnt a lot already trying to figure this out. This is my first dip into IC's and circuit based logic. And really feel I have made progress, esp in understanding how little I know



I think my inexperience is culprit in not understanding the solutions presented. And I appreciate the help.



Now the power on state of the latch will have either R = 0 & S = 0

Or R=1 & S = 0, The problem is when when R = S = 0 and then the latch jumps into its race condition.



Not sure how a power on reset would work here, but I can understand putting a delay in between Q and S would yield the result I am looking for. And I would hope that it will initialize the latch with 'Q as high R=S=0.



Now, would a recommended method of doing this would be to put a capacitor on the Q,S link and ground. Would this slow down the race condition enough to allow the latch to initialize in the state I wish? Or is there another expected method used to cause this slow down?



For the explicit reset circuit, if one loses power. Regains power and once you are above the threshold and have proper power. How would the reset circuit integrate with the inputs on the latches, would it just trigger transistors on the RS inputs? Or would it have them in the way of the QS and 'QR pathways?

Because if its simply Preventing the input on the RS side, won't I have the same race condition of the RS latch being R=S=0 and then one side "winning" the race condition.



- E

And after typing up the reply I tried using a 1.8 uF ceramic capacitor on the path between Q and the other input on the S NOR and ground.

And it starts up in the state I want/expect every time. I will have to tweak and see what value capacitor works best, as I think 1.8 uF is a little large but I don't have a background as to why that is just its physical size seems excessive.(Or I have a large capacitor, rated for 630v)

But still curious as to how the other methods would affect this circuitry.

Seems like it was such a simple solution (if correct) but something I was simply unaware of.

- E

 

[John Larkin]

On Tue, 13 Aug 2013 20:38:57 -0700, miso <miso@sushi.com> wrote:

If you are using off the shelf controllers, I'm not so sure this
workshop is really needed. If you are rolling your own switchers, well
you shouldn't be.

Why not? Who wants to just copy eval boards?

And with digital power coming along, designing your own switcher may be the new
thing.


--

John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

 

[Tim Wescott]

On Tue, 13 Aug 2013 22:08:50 -0700, eric wrote:

I have been all over the place and cannot seem to find an actual
explanation for one or many possible solutions on the race state of a SR
Latch on initialization/power up

I have a small circuit on a bread board using an SR Latch, the circuit
functions correctly once power is on and the SR latch has been manually
used to set the desired initial state.

But, the race condition when the circuit is powered is very
indeterminate and it bounces back and forth to which state wins. But I
cannot seem to find an explanation as to how to set the initial state
properly and then have it function as normal.

I have tried a few methods on my own but none seem reliable enough. Am I
missing something as it seems like it should be quite simple, but I have
not seen a solution I can apply on my board. Either I'm blind and its
right in front of my face or somehow I have been unable to Google it.
Found a LOT of sites explaining the race condition, but no solutions on
how to "set" it.

Flip flops come up in indeterminate states unless you do something
explicit to reset them, or as Jan suggested, to make one input come up
slower than the other.

Because a symmetrical flip-flop that happens to be half way between a 0
state and a 1 state is inherently indeterminate as to which direction its
going to go, you're pretty much doomed to this problem unless you do
something about it.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

 

[Jim Thompson]

On Wed, 14 Aug 2013 11:34:20 -0500, Tim Wescott
<tim@seemywebsite.really> wrote:

On Tue, 13 Aug 2013 22:08:50 -0700, eric wrote:

I have been all over the place and cannot seem to find an actual
explanation for one or many possible solutions on the race state of a SR
Latch on initialization/power up

I have a small circuit on a bread board using an SR Latch, the circuit
functions correctly once power is on and the SR latch has been manually
used to set the desired initial state.

But, the race condition when the circuit is powered is very
indeterminate and it bounces back and forth to which state wins. But I
cannot seem to find an explanation as to how to set the initial state
properly and then have it function as normal.

I have tried a few methods on my own but none seem reliable enough. Am I
missing something as it seems like it should be quite simple, but I have
not seen a solution I can apply on my board. Either I'm blind and its
right in front of my face or somehow I have been unable to Google it.
Found a LOT of sites explaining the race condition, but no solutions on
how to "set" it.

Flip flops come up in indeterminate states unless you do something
explicit to reset them, or as Jan suggested, to make one input come up
slower than the other.

Because a symmetrical flip-flop that happens to be half way between a 0
state and a 1 state is inherently indeterminate as to which direction its
going to go, you're pretty much doomed to this problem unless you do
something about it.

Use a good POR (power-on-reset) circuit that also copes with
brown-outs.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[panfilero]

On Wednesday, August 14, 2013 12:08:50 AM UTC-5, er...@bauld.com wrote:

I have been all over the place and cannot seem to find an actual explanation for one or many possible solutions on the race state of a SR Latch on initialization/power up



I have a small circuit on a bread board using an SR Latch, the circuit functions correctly once power is on and the SR latch has been manually used to set the desired initial state.



But, the race condition when the circuit is powered is very indeterminate and it bounces back and forth to which state wins. But I cannot seem to find an explanation as to how to set the initial state properly and then have it function as normal.



I have tried a few methods on my own but none seem reliable enough. Am I missing something as it seems like it should be quite simple, but I have not seen a solution I can apply on my board. Either I'm blind and its right in front of my face or somehow I have been unable to Google it. Found a LOT of sites explaining the race condition, but no solutions on how to "set" it..



-E

Assuming it has an Active Low reset pin, could you tie its Reset to ground through a large cap and series resistor, that way when you boot up the reset pin will be held low until the cap charges up enough to decouple the reset pin from ground?

 

On Wednesday, August 14, 2013 1:45:16 PM UTC-7, panfilero wrote:

On Wednesday, August 14, 2013 12:08:50 AM UTC-5, er...@bauld.com wrote:

I have been all over the place and cannot seem to find an actual explanation for one or many possible solutions on the race state of a SR Latch on initialization/power up







I have a small circuit on a bread board using an SR Latch, the circuit functions correctly once power is on and the SR latch has been manually used to set the desired initial state.







But, the race condition when the circuit is powered is very indeterminate and it bounces back and forth to which state wins. But I cannot seem to find an explanation as to how to set the initial state properly and then have it function as normal.







I have tried a few methods on my own but none seem reliable enough. Am I missing something as it seems like it should be quite simple, but I have not seen a solution I can apply on my board. Either I'm blind and its right in front of my face or somehow I have been unable to Google it. Found a LOT of sites explaining the race condition, but no solutions on how to "set" it.







-E



Assuming it has an Active Low reset pin, could you tie its Reset to ground through a large cap and series resistor, that way when you boot up the reset pin will be held low until the cap charges up enough to decouple the reset pin from ground?

There is no reset pin I am aware of, the SR Latch is constructed from two NOR gates on a quad input NOR gate IC.
If the latch was fully embedded into a IC instead of constructed from two NOR gates.. not sure I understand how the reset works in that case. Do you know of a chip that has that functionality? Just so I can see it and try to figure out how that relates to what was previously brought up.

-E

 

On Tuesday, August 13, 2013 6:38:56 PM UTC-4, panfilero wrote:

I found this power supply design workshop on the web, I thought it sounded pretty good and am entertaining the idea of signing up for it. I've never attended a workshop like this before, and it is a bit pricey. I was wondering what people's thoughts are on workshops, or if this workshop sounds good? I'm fairly new (less than 5 years) to power supply design and want to learn more about it, I've designed a few, I'm familiar with the topologies, wrestle through compensation and magnetics design. A link to the workshop is below. thanks



http://www.ridleyengineering.com/workshops.html

I don't know where you live but this one is free.

http://www.arrownac.com/offers/vision-2013/

 

[Joerg]

miso wrote:

If you are using off the shelf controllers, I'm not so sure this
workshop is really needed. ...

Off-the-shelf controllers teach you nothing about the magnetics,
intracacies of capacitors, things like that. Heck, they don't even tell
you how an LC post-filter somewhere down the line can cause the whole
chebang to go berserk. If someone isn't very familiar with all that
(usually via blood, sweat and tears) such a workshop can be very worthwhile.

... If you are rolling your own switchers, well you shouldn't be.

Almost anyone who has ever designed under super-tight budget for
consumer gear will know otherwise. One of my early cases was when a new
client had a working design but Maxim could not furnish production
quantities of their MAX770. No surprise there. Since there wasn't any
competing part with similar performance and price I ripped it all out,
designed my own discrete solution, with current mode control and all,
and that is still in production.

--
Regards, Joerg

http://www.analogconsultants.com/

 

[miso]

On 8/14/2013 8:53 AM, John Larkin wrote:

On Tue, 13 Aug 2013 20:38:57 -0700, miso <miso@sushi.com> wrote:


If you are using off the shelf controllers, I'm not so sure this
workshop is really needed. If you are rolling your own switchers, well
you shouldn't be.


Why not? Who wants to just copy eval boards?

And with digital power coming along, designing your own switcher may be the new
thing.

Uh, because eval boards are designed to provide good working circuits.
Yes, a novel idea.

You do realize a chip all by its lonesome is way more reliable than
something that uses firmware to run.

 

[miso]

On 8/14/2013 10:19 AM, Joerg wrote:

miso wrote:

If you are using off the shelf controllers, I'm not so sure this
workshop is really needed. ...


Off-the-shelf controllers teach you nothing about the magnetics,
intracacies of capacitors, things like that. Heck, they don't even tell
you how an LC post-filter somewhere down the line can cause the whole
chebang to go berserk. If someone isn't very familiar with all that
(usually via blood, sweat and tears) such a workshop can be very worthwhile.


... If you are rolling your own switchers, well you shouldn't be.


Almost anyone who has ever designed under super-tight budget for
consumer gear will know otherwise. One of my early cases was when a new
client had a working design but Maxim could not furnish production
quantities of their MAX770. No surprise there. Since there wasn't any
competing part with similar performance and price I ripped it all out,
designed my own discrete solution, with current mode control and all,
and that is still in production.

Funny how these cellphone manufacturers manage to source controller
chips. Well I guess some people know how to run a business.